我现在做的项目里，要用四片ddr2做存储,xilinx v6 lx240t fpga，我用ise 13.1的iP coregen 产生了mig核，我在工程里例化了四个mig核，mig核输入时钟是单端的，板子外部给的时钟是200MHZ,我现在是把200MHZ 经过ibufg 后，经过dcm 产生了mig的sys_clk和clk_ref,然后把这两个时钟接到mig核上，但是布局布线不通过，所以也没有bit文件产生，好头疼，有没有什么办法吆，下面是ise给的提示信息
WARNING:Place:1152 - Unroutable Placement! A MMCM / MMCM clock component pair have been found that are not placed at a
   routable MMCM driver / load site pair. The driver MMCM component <u_clk/u_dcm1/mmcm_adv_inst> is placed at site
   <MMCM_ADV_X0Y10>. The load MMCM component <u_mig_37_3/u_infrastructure/u_mmcm_adv> is placed at site <MMCM_ADV_X0Y1>.
   The pair can use the fast path between them if they are both placed in the same horizontal clock region pair. You may
   want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE
   constraint was applied on COMP.PIN <u_clk/u_dcm1/mmcm_adv_inst.CLKOUT0> allowing your design to continue. This
   constraint disables all clock placer rules related to the specified COMP.PIN. This placement is UNROUTABLE in PAR and
   therefore, this error condition should be fixed in your design.