用ISE10.1做布局时出现以下警告：
"Autotimespec constraint for clock net  clk"fails the maximum period check for input clock "clk" to DCM_ADV block"instance_name/DCM_ADV_INST"because the period constraint value(1000ps)excceds the maximum internal period limit of 4168ps.please reduce the period of the constraint to remove this timing failure.
就是我用DCM时时钟输入600MHz时出现上述警告，我用的是V5。
请问怎样去减小这个周期约束呢？我的ucf里没加任何约束，这里的约束是自动生成的？DCM里的参数应该不能随便改吧？