本帖最后由 crjab 于 2013-7-19 16:33 编辑

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity erfen is
port
(
clock:in std_logic;
clkout:out std_logic
);
end erfen;

architecture Behavioral of erfen is
signal clk:std_logic:='0';
begin
process(clock)
begin
if rising_edge(clock) then
clk<=not clk;
end if;
end process;
clkout<=clk;
end Behavioral;
以上是最简单的一个分频电路程序，其测试文件如下：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY erfentest IS
END erfentest;

ARCHITECTURE behavior OF erfentest IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT erfen
    PORT(
         clock : IN  std_logic;
         clkout : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal clock : std_logic;

         --Outputs
   signal clkout : std_logic;

   -- Clock period definitions
   constant clock_period : time := 1us;
   constant clkout_period : time := 1us;

BEGIN

        -- Instantiate the Unit Under Test (UUT)
   uut: erfen PORT MAP (
          clock => clock,
          clkout => clkout
        );
   -- Clock process definitions
   clock_process :process
   begin
                clock <= '0';
                wait for clock_period/2;
                clock <= '1';
                wait for clock_period/2;
   end process;

   clkout_process :process
   begin
                clkout <= '0';
                wait for clkout_period/2;
                clkout <= '1';
                wait for clkout_period/2;
   end process;
END;

得出的波形却是这样：（附件里）
请高手看看怎么回事，，，刚接触这块，连一个小小的仿真都没搞定，打击很大啊