FPGA

寮傛FIFO鐨刅erilog瀹炵幇瀹炰緥鍒嗘瀽

2020-02-28 18:25发布

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鏈笘鏈€鍚庣敱 wmsk 浜?2013-1-22 11:36 缂栬緫

//----------------------STYLE #1--------------------------module fifo1(rdata, wfull, rempty, wdata, winc, wclk, wrst_n,rinc, rclk, rrst_n);parameter DSIZE = 8;parameter ASIZE = 4;output [DSIZE-1:0] rdata;output wfull;output rempty;input [DSIZE-1:0] wdata;input winc, wclk, wrst_n;input rinc, rclk, rrst_n;reg wfull,rempty;reg [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr, wq1_rptr,rq1_wptr;reg [ASIZE:0] rbin, wbin;reg [DSIZE-1:0] mem[0 : (1<<ASIZE)-1];wire [ASIZE-1:0] waddr, raddr;wire [ASIZE:0] rgraynext, rbinnext,wgraynext,wbinnext;wire rempty_val,wfull_val;//-----------------鍙屽彛RAM瀛樺偍鍣?-------------------assign rdata=mem[raddr];always@(posedge wclk)if (winc && !wfull) mem[waddr] <= wdata;//-------------鍚屾rptr 鎸囬拡-------------------------always @(posedge wclk or negedge wrst_n)if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};//-------------鍚屾wptr鎸囬拡---------------------------always @(posedge rclk or negedge rrst_n)if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};//-------------rempty浜х敓涓巖addr浜х敓-------------------//-------------------// GRAYSTYLE2 pointer//-------------------always @(posedge rclk or negedge rrst_n)beginif (!rrst_n) {rbin, rptr} <= 0;else {rbin, rptr} <= {rbinnext, rgraynext};end// Memory read-address pointer (okay to use binary to address memory)assign raddr = rbin[ASIZE-1:0];assign rbinnext = rbin + (rinc & ~rempty);assign rgraynext = (rbinnext>>1) ^ rbinnext;//---------------------------------------------------------------// FIFO empty when the next rptr == synchronized wptr or on reset//---------------------------------------------------------------assign rempty_val = (rgraynext == rq2_wptr);always @(posedge rclk or negedge rrst_n)beginif (!rrst_n) rempty <= 1'b1;else rempty <= rempty_val;end//---------------wfull浜х敓涓巜addr浜х敓------------------------------// GRAYSTYLE2 pointeralways @(posedge wclk or negedge wrst_n)if (!wrst_n) {wbin, wptr} <= 0;else {wbin, wptr} <= {wbinnext, wgraynext};// Memory write-address pointer (okay to use binary to address memory)assign waddr = wbin[ASIZE-1:0];assign wbinnext = wbin + (winc & ~wfull);assign wgraynext = (wbinnext>>1) ^ wbinnext;//------------------------------------------------------------------// Simplified version of the three necessary full-tests:// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));//------------------------------------------------------------------assign wfull_val = (wgraynext=={~wq2_rptr[ASIZE:ASIZE-1],wq2_rptr[ASIZE-2:0]});always @(posedge wclk or negedge wrst_n)if (!wrst_n) wfull <= 1'b0;else wfull <= wfull_val;endmodule
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vincentyeh
2020-02-29 10:24
AL460 Full HD FIFO DRAM 鐨勫熀鏈粨鏋凢IFO(First in First out) 绗﹀悎楂橀€熷奖鍍忓厛杩涘厛鍑虹殑缁撴瀯锛屽挨鍏堕€傜敤浜庢暟鐮佸奖鍍忚祫鏂欑殑鏆傚瓨鍣ㄤ娇鐢ㄣ€?br /> 涓€锛庣嫭绔嬬殑鍐欏叆/ 杈撳嚭绋嬪簭锛岃緝浣庣殑杈撳叆clock rate,鍙湁鏁堝湴涓鸿吹鍙哥畝鍖栧紑鍙戞垚鏈互鍙婃椂闂淬€?br /> 浜岋紟鏀彺褰卞儚/鍥惧儚鏁颁綅璧勬枡VGA鍒?080p,鍐呴儴鏋舵瀯涓?Mx 16bit璁板繂浣撴灦鏋勶紝鏈€楂橀€熷害鍙揪鍒?50MHz,鍙弧瓒?080p鐨勮璁￠渶姹傘€?br /> 涓夛紟鍏锋湁杈撳叆/杈撳嚭鏅鸿兘鎺у埗(enable control) , 鍙仛鍙屽€嶈蹇嗕綋(double buffer)鎺у埗锛屽湪frame 鍥炬鎺у埗缂栫▼涓婂挨鍏舵柟渚裤€?br />

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