本帖最后由 damoyeren 于 2013-7-26 18:06 编辑

1.本程序30个警告。分析出错警告原因？
2.程序模仿郭天祥CPLD中对AD的操作，将AD采集电压用0-255个数字表示。

--库的调用
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--实体定义
entity ADC0804 is
port(rst:in std_logic;
     clk:in std_logic;
     data_in:in std_logic_vector(7 downto 0);
     data_o: out std_logic_vector(7 downto 0);
     l:out std_logic_vector(5 downto 0);
     wr:out std_logic;
     rd:out std_logic;
     cs:out std_logic;
     intr:in std_logic);
end ADC0804;
architecture rtl of ADC0804 is
type state is (start,conversion,read1,read2);
signal current_state,next_state:state:=start;
signal clock:std_logic;
signal p:integer range 0 to 255;
signal b0,b1,b2:integer range 0 to 9;
signal cnt:integer range 0 to 3;
begin
                  --分频进程
  process(clk)
variable cnt1:integer range 0 to 200;
variable cnt2:integer range 0 to 10;
  begin
if clk'event and clk='1'then
  if cnt1=200 then
   cnt1:=0;
   if cnt2=10 then
    cnt2:=0;
    clock<=not clock;
    if cnt=3 then
     cnt<=0;
     else
    cnt<=cnt+1;
    end if;
   else
   cnt2:=cnt2+1;
   end if;
  else
   cnt1:=cnt1+1;
  end if;
end if;
  end process;
                 --显示进程
   process(p,clk)
   begin
   case p is
            when 0|10|20|30|40|50|60|70|80|90|100|110|120|130|140|150|160|170|180|190|200|210|220|230|240|250=>b0<=0;
   when 1|11|21|31|41|51|61|71|81|91|101|111|121|131|141|151|161|171|181|191|201|211|221|231|241|251=>b0<=1;
   when 2|12|22|32|42|52|62|72|82|92|102|112|122|132|142|152|162|172|182|192|202|212|222|232|242|252=>b0<=2;
   when 3|13|23|33|43|53|63|73|83|93|103|113|123|133|143|153|163|173|183|193|203|213|223|233|243|253=>b0<=3;
   when 4|14|24|34|44|54|64|74|84|94|104|114|124|134|144|154|164|174|184|194|204|214|224|234|244|254=>b0<=4;
   when 5|15|25|35|45|55|65|75|85|95|105|115|125|135|145|155|165|175|185|195|205|215|225|235|245|255=>b0<=5;
   when 6|16|26|36|46|56|66|76|86|96|106|116|126|136|146|156|166|176|186|196|206|216|226|236|246=>b0<=6;
   when 7|17|27|37|47|57|67|77|87|97|107|117|127|137|147|157|167|177|187|197|207|217|227|237|247=>b0<=7;
   when 8|18|28|38|48|58|68|78|88|98|108|118|128|138|148|158|168|178|188|198|208|218|228|238|248=>b0<=8;
   when 9|19|29|39|49|59|69|79|89|99|109|119|129|139|149|159|169|179|189|199|209|219|229|239|249=>b0<=9;
   when others=>NULL;
  end case;
  
  case p is
   when 0|1|2|3|4|5|6|7|8|9|100|101|102|103|104|105|106|107|108|109|200|201|202|203|204|205|206|207|208|209=>b1<=0;
   when 10|11|12|13|14|15|16|17|18|19|110|111|112|113|114|115|116|117|118|119|210|211|212|213|214|215|216|217|218|219=>b1<=1;
   when 20|21|22|23|24|25|26|27|28|29|120|121|122|123|124|125|126|127|128|129|220|221|222|223|224|225|226|227|228|229=>b1<=2;
   when 30|31|32|33|34|35|36|37|38|39|130|131|132|133|134|135|136|137|138|139|230|231|232|233|234|235|236|237|238|239=>b1<=3;
   when 40|41|42|43|44|45|46|47|48|49|140|141|142|143|144|145|146|147|148|149|240|241|242|243|244|245|246|247|248|249=>b1<=4;   
   when 50|51|52|53|54|55|56|57|58|59|150|151|152|153|154|155|156|157|158|159|250|251|252|253|254|255=>b1<=5;
   when 60|61|62|63|64|65|66|67|68|69|160|161|162|163|164|165|166|167|168|169=>b1<=6;
   when 70|71|72|73|74|75|76|77|78|79|170|171|172|173|174|175|176|177|178|179=>b1<=7;
   when 80|81|82|83|84|85|86|87|88|89|180|181|182|183|184|185|186|187|188|189=>b1<=8;
   when 90|91|92|93|94|95|96|97|98|99|190|191|192|193|194|195|196|197|198|199=>b1<=9;
   when others=>NULL;
  end case;
  if p<100 then
   b2<=0;
      if p>100 and p<200 then
    b2<=1;
   else
   b2<=2;
   end if;
  end if;
end process;
    --状态转换进程
process(clock,rst)
begin
  current_state<=start;
   if clock='1' then
   current_state<=next_state;
   end if;
end process;
          --驱动进程
process(intr,next_state)
begin
case current_state is
  when start=>cs<='0';rd<='0';wr<='1';--开始转换
              next_state<=conversion;
  when conversion=>
               cs<='1';rd<='1';wr<='1';--正在转换
               next_state<=read1;
  when read1=>if intr='1' then--读取标志位
               next_state<=conversion;
           else
         cs<='0';wr<='1';rd<='0';
         next_state<=read2;
     end if;
  when read2=>cs<='1';wr<='1';rd<='1';--读取转换数据
              next_state<=start;
        when others=>NULL;
     end case;
     end process;
     -------------------读取转换数据--------------
   process(clock,rst)
   begin
   if rst='0' then
  p<=0;
  if clock='1' then
   p<=conv_integer(data_in);
   end if;
   end if;
   end process;
   ----------------------------------------------------
     --显示进程
   process(cnt)
    function b_t0_s7 (bcd8421:integer range 0 to 9)return std_logic_vector is
       VARIABLE smg7: STD_LOGIC_VECTOR(7 DOWNTO 0);
    begin
  case bcd8421 is
     when 0 => smg7:="11111100";
     WHEN 1 => smg7:="01100000";
     WHEN 2 => smg7:="11011010";
     WHEN 3 => smg7:="11110010";
     WHEN 4 => smg7:="01100110";
     WHEN 5 => smg7:="10110110";
     WHEN 6 => smg7:="10111110";
     WHEN 7 => smg7:="11100000";
     WHEN 8 => smg7:="11111110";
     WHEN 9 => smg7:="11110110";
     WHEN OTHERS=>smg7:="10001110";
  end case;
  return smg7;
  end  b_t0_s7;
   begin
    case cnt is
     when 0 => l<="111110";data_o<=b_t0_s7(b0);
     when 1 => l<="111101";data_o<=b_t0_s7(b1);
    when 2 => l<="111011";data_o<=b_t0_s7(b2);
    when others=>l<="111111";
   end case;
end process;
end rtl;


Warning (10631): VHDL Process Statement warning at ADC0804.vhd(52): inferring latch(es) for signal or variable "b2", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at ADC0804.vhd(95): signal "next_state" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ADC0804.vhd(101): signal "current_state" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at ADC0804.vhd(99): inferring latch(es) for signal or variable "cs", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ADC0804.vhd(99): inferring latch(es) for signal or variable "rd", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ADC0804.vhd(99): inferring latch(es) for signal or variable "wr", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at ADC0804.vhd(124): signal "data_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at ADC0804.vhd(119): inferring latch(es) for signal or variable "p", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at ADC0804.vhd(151): signal "b0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ADC0804.vhd(152): signal "b1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at ADC0804.vhd(153): signal "b2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at ADC0804.vhd(130): inferring latch(es) for signal or variable "data_o", which holds its previous value in one or more paths through the process
Warning: Latch data_o[1]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal cnt[0]
Warning: Latch data_o[2]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal cnt[0]
Warning: Latch data_o[3]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal cnt[1]
Warning: Latch data_o[4]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal cnt[0]
Warning: Latch data_o[5]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal cnt[0]
Warning: Latch data_o[6]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal cnt[1]
Warning: Latch data_o[7]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal cnt[0]
Warning: Latch b2[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal p[7]
Warning: Latch b2[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal p[7]
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "data_o[0]" is stuck at GND
Warning (13410): Pin "l[3]" is stuck at VCC
Warning (13410): Pin "l[4]" is stuck at VCC
Warning (13410): Pin "l[5]" is stuck at VCC
Warning (13410): Pin "wr" is stuck at VCC
Warning (13410): Pin "rd" is stuck at GND
Warning (13410): Pin "cs" is stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "intr"
Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "p[2]" is a latch
Warning: Node "p[6]" is a latch
Warning: Node "p[4]" is a latch
Warning: Node "p[5]" is a latch
Warning: Node "p[1]" is a latch
Warning: Node "p[7]" is a latch
Warning: Node "p[3]" is a latch
Warning: Node "p[0]" is a latch
Warning: Node "b2[1]" is a latch
Warning: Node "b2[0]" is a latch
Warning: Node "data_o[1]$latch" is a latch
Warning: Node "data_o[2]$latch" is a latch
Warning: Node "data_o[3]$latch" is a latch
Warning: Node "data_o[4]$latch" is a latch
Warning: Node "data_o[5]$latch" is a latch
Warning: Node "data_o[6]$latch" is a latch
Warning: Node "data_o[7]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Assuming node "rst" is a latch enable. Will not compute fmax for this pin.
Warning: Found 12 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "p[3]" as buffer
Info: Detected ripple clock "p[7]" as buffer
Info: Detected ripple clock "p[5]" as buffer
Info: Detected ripple clock "p[4]" as buffer
Info: Detected ripple clock "p[6]" as buffer
Info: Detected ripple clock "p[2]" as buffer
Info: Detected gated clock "LessThan0~0" as buffer
Info: Detected gated clock "LessThan0~1" as buffer
Info: Detected gated clock "LessThan0~2" as buffer
Info: Detected gated clock "Mux39~0" as buffer
Info: Detected ripple clock "cnt[1]" as buffer
Info: Detected ripple clock "cnt[0]" as buffer
Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock "rst" with clock skew larger than data delay. See Compilation Report for details.