interrupt void scibTxFifoIsr(void)
{
Uint16 i;
// if(Receive_flag==1)
// {
for(i=0; i< 8; i++)
{
ScibRegs.SCITXBUF=0x0f;//sdataB[i]; // Send data
}
// Receive_flag=0;
// }
// for(i=0; i< 8; i++) //Increment send data for next cycle
// {
// sdataB[i] = (sdataB[i]-1) & 0x00FF;
// }
ScibRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK
}
interrupt void scibRxFifoIsr(void)
{
// Uint16 i=0;
// for(i=0;i<8;i++)
// {
rdataB[0]=ScibRegs.SCIRXBUF.all; // Read data
// }
// Receive_flag=1;
// for(i=0;i<8;i++) // Check received data
// {
// if(rdataB[i] != ( (rdata_pointB-i) & 0x00FF) ) error();
// }
// rdata_pointB = (rdata_pointB-1) & 0x00FF;
ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
ScibRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack
}
void scib_fifo_init()
{
ScibRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
ScibRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
ScibRegs.SCICTL2.bit.TXINTENA =1;
ScibRegs.SCICTL2.bit.RXBKINTENA =1;
ScibRegs.SCIHBAUD =0x0001;
ScibRegs.SCILBAUD =0x00E7;//SCI_PRD;
ScibRegs.SCICCR.bit.LOOPBKENA =0; // Enable loop back
ScibRegs.SCIFFTX.all=0xC028;
ScibRegs.SCIFFRX.all=0x0021;
ScibRegs.SCIFFCT.all=0x00;
ScibRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;
ScibRegs.SCIFFRX.bit.RXFIFORESET=1;
}
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