#include <msp430f5529.h>
#define CPU_F ((double)12000000)
#define delay_us(x) __delay_cycles((long)(CPU_F*(double)x/1000000.0))
#define delay_ms(x) __delay_cycles((long)(CPU_F*(double)x/1000.0))
#define Num_of_Results 4
//volatile unsigned int A0results[Num_of_Results];
//volatile unsigned int A1results[Num_of_Results];
volatile unsigned int A2results[Num_of_Results];
volatile unsigned int A3results[Num_of_Results];
unsigned char index=0,i=0,j=0,ok=0;
unsigned int k=0,q=0;
unsigned int Current[1205],Voltage[1205];
unsigned char Voltage_Buffer[6];
unsigned char Current_Buffer[6];
unsigned char Send_num=0;
unsigned char Send_num_buffer[4];
unsigned int Volt=0;
signed char yes=0;
unsigned long int time_num=0;
unsigned char time_num_Buffer[3];
void Clock_Init(void);
void AD_init();
void UART_init();
void USCI_A0_PutChar(char Chr);
char USCI_A0_GetChar(void);
void Uart_Send(unsigned char *s);
void Timer(void);
void main(void)
{
WDTCTL = WDTPW+WDTHOLD;
Clock_Init();
AD_init();
UART_init();
Timer();
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, Enable interrupts
__no_operation(); // For debugger
}
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
{
switch(__even_in_range(ADC12IV,34))
{
case 0: break; // Vector 0: No interrupt
case 2: break; // Vector 2: ADC overflow
case 4: break; // Vector 4: ADC timing overflow
case 6: break; // Vector 6: ADC12IFG0
case 8: break; // Vector 8: ADC12IFG1
case 10: break; // Vector 10: ADC12IFG2
case 12:
{
// A0results[index] = ADC12MEM0; // Move A0 results, IFG is cleared
// A1results[index] = ADC12MEM1; // Move A1 results, IFG is cleared
A2results[index] = ADC12MEM2; // Move A0 results, IFG is cleared
A3results[index] = ADC12MEM3; // Move A1 results, IFG is cleared
index++; // Increment results index, modulo; Set Breakpoint1 here
//
// Current[k]=A2results[0];
// Voltage[k]=A3results[0];
if (index == 2)
{
index = 0;
Voltage[k]=0;
Current[k]=0;
for(i=0;i<2;i++)
{
Current[k]+=A3results
;
Voltage[k]+=A2results;
}
if(ok==1)
{
k++;
}
else
{
if(Voltage[k]>100)
{
yes++;
if(yes>5)
yes=5;
}
else
{
yes--;
if(yes<0)
yes=0;
}
if(yes>3)
{
yes=0;
ok=1;
}
}
}
if(k>1200)
{
k=0;
ADC12CTL0 &=~ ADC12ENC;
ADC12CTL0 &=~ ADC12SC; // Start convn - software trigger
// TB0CCTL0 &=~CCIE;
Uart_Send("
");
Uart_Send("*********************************
");
Send_num++;
Send_num_buffer[0]= ((Send_num/100)+0x30);
Send_num_buffer[1]= ((Send_num%100/10)+0x30);
Send_num_buffer[2]= ((Send_num%10)+0x30);
Send_num_buffer[3]= ' ';
Uart_Send(Send_num_buffer);
Uart_Send(" start !
");
Uart_Send("U(V), I(A)
");
for(q=1;q<=1200;q++)
{
Voltage[q]=Voltage[q]*10/132;
Current[q]= Current[q]*10/74.5;
Voltage_Buffer[0]= ((Voltage[q]/1000)+0x30);
Voltage_Buffer[1]= ((Voltage[q]%1000/100)+0x30);
Voltage_Buffer[2]= ((Voltage[q]%100/10)+0x30);
Voltage_Buffer[3]= ('.');
Voltage_Buffer[4]= ((Voltage[q]%100%10)+0x30);
Voltage_Buffer[5]= ' ';
Uart_Send(Voltage_Buffer);
Uart_Send(", ");
Current_Buffer[0]= ((Current[q]/1000)+0x30);
Current_Buffer[1]= ((Current[q]%1000/100)+0x30);
Current_Buffer[2]= ('.');
Current_Buffer[3]= ((Current[q]%100/10)+0x30);
Current_Buffer[4]= ((Current[q]%100%10)+0x30);
Current_Buffer[5]= ' ';
Uart_Send(Current_Buffer);
Uart_Send("
");
}
Uart_Send("
");
Uart_Send(Send_num_buffer);
Uart_Send(" end !
");
// Uart_Send("time interval is :");
// time_num=time_num/1.2;
// time_num_Buffer[0]= ((time_num/100)+0x30);
// time_num_Buffer[1]= ((time_num%100/10)+0x30);
// time_num_Buffer[2]= ((time_num%10)+0x30);
// Uart_Send(time_num_Buffer);
// Uart_Send(" us
");
Uart_Send("*********************************
");
}
} break; // Vector 12: ADC12IFG3
case 14: break; // Vector 14: ADC12IFG4
case 16: break; // Vector 16: ADC12IFG5
case 18: break; // Vector 18: ADC12IFG6
case 20: break; // Vector 20: ADC12IFG7
case 22: break; // Vector 22: ADC12IFG8
case 24: break; // Vector 24: ADC12IFG9
case 26: break; // Vector 26: ADC12IFG10
case 28: break; // Vector 28: ADC12IFG11
case 30: break; // Vector 30: ADC12IFG12
case 32: break; // Vector 32: ADC12IFG13
case 34: break; // Vector 34: ADC12IFG14
default: break;
}
}
// Echo back RXed character, confirm TX buffer is ready first
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2:
{ // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
// UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
ok=0;
k=0;
yes=0;
index = 0;
ADC12CTL0 |= ADC12ENC; // Enable conversions
ADC12CTL0 |= ADC12SC; // Start convn - software trigger
// TB0CCTL0 |= CCIE;
// TB0CTL |= TBCLR;
}
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
void Timer(void)
{
TB0CCTL0&=~ CCIE; // CCR0 interrupt enabled
TB0CCR0 = 12000;
TB0CTL = TBSSEL_2 + MC_1 + TBCLR; // SMCLK, contmode, clear TAR
}
// Timer2 interrupt service routine
#pragma vector=TIMER0_B0_VECTOR
__interrupt void TIMER0_B0_ISR(void)
{
time_num++;
}
void AD_init()
{
P6SEL |= 0x0f; // Enable A/D channel inputs
REFCTL0 &= ~REFMSTR;
ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_4+ADC12REFON;//+ADC12REF2_5V; // Turn on ADC12, extend sampling time
// to avoid overflow of results
ADC12CTL1 =ADC12CSTARTADD_2+ADC12SHP+ADC12CONSEQ_3+ADC12SSEL_3; // Use sampling timer, repeated sequence
// ADC12CTL2 |= ADC12PDIV;
// ADC12MCTL0 = ADC12INCH_0; // ref+=AVcc, channel = A0
// ADC12MCTL1 = ADC12INCH_1; // ref+=AVcc, channel = A1
ADC12MCTL2 = ADC12INCH_2;//+ADC12SREF_1; // ref+=AVcc, channel = A2
ADC12MCTL3 = ADC12INCH_3+ADC12EOS;//+ADC12SREF_1; // ref+=AVcc, channel = A3, end seq.
ADC12IE = 0x08; // Enable ADC12IFG.3
// ADC12CTL0 |= ADC12ENC; // Enable conversions
// ADC12CTL0 |= ADC12SC; // Start convn - software trigger
}
void Clock_Init(void) // ACLK = REFO = 32kHz, MCLK = SMCLK = 8MHz
{
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
}
void UART_init()
{
P3SEL = BIT3+BIT4; // P3.4,5 = USCI_A0 TXD/RXD
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 78; // 1MHz 9600 (see User's Guide)
UCA0BR1 = 0; // 1MHz 9600
UCA0MCTL = UCBRS_0 + UCBRF_2 + UCOS16; // Modln UCBRSx=0, UCBRFx=0,
// over sampling
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
}
void USCI_A0_PutChar(char Chr)
{
UCA0TXBUF=Chr;
while (!(UCA0IFG & UCTXIFG));
}
char USCI_A0_GetChar(void)
{
while(!(UCA0IFG & UCRXIFG));
return (UCA0RXBUF);
}
void Uart_Send(unsigned char *s)
{
while(*s > 0)
{
USCI_A0_PutChar(*s);
s++;
}
}
此帖出自
小平头技术问答
一周热门 更多>