FPGA：Kintex7, 输入为差分时钟 200M
ip 核实例
      myclc_test instance_name
   (// Clock in ports
    .CLK_IN1_P(clk_in_p),    // IN
    .CLK_IN1_N(clk_in_n),    // IN
    // Clock out ports
    .CLK_OUT1(CLK_OUT1),     // OUT
    // Status and control signals
    .RESET(rst),// IN
    .LOCKED(rst_n));      // OUT

UCF约束
   时序约束
NET "clk_in_p" TNM_NET = "clk_in_p";
tiMESPEC "TS_clk_in_p" = PERIOD : "clk_in_p" : 5.000 ns HIGH 50.0%;
管脚约束
NET "clk_in_p"   LOC="AA3" |IOSTANDARD=DIFF_SSTL15;
NET "clk_in_n"   LOC="AA2" |IOSTANDARD=DIFF_SSTL15;

结果  CLK_OUT1恒为零
请问原因何在？<p>