FPGA

FPGA配置AD9364怎么操作

2019-07-15 20:48发布

站内问答 / FPGA
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有配置文件如下：
//************************************************************
// AD9361 R2 Auto Generated Initialization Script:  This script was
// generated using the AD9361 Customer software Version 2.1.3
//************************************************************
// Profile: LTE 10 MHz
// REFCLK_IN: 40.000 MHz


RESET_FPGA
RESET_DUT


BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz
SPIWrite 3DF,01 // Required for proper operation
ReadPartNumber
SPIWrite 2A6,0E // Enable Master Bias
SPIWrite 2A8,0E // Set Bandgap Trim
REFCLK_Scale 40.000000,1,2 // Sets local variables in script engine, user can ignore
SPIWrite 292,08 // Set DCXO Coarse Tune[5:0].  Coarse and Fine nominal values used with eval system.  Other nominal values may be needed in a customer system
SPIWrite 293,80 // Set DCXO Fine Tune [12:5]
SPIWrite 294,00 // Set DCXO Fine Tune [4:0]
SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 009,07 // Enable Clocks
WAIT 20 // waits 20 ms


//************************************************************
// Set BBPLL Frequency: 983.040000
//************************************************************
SPIWrite 045,00 // Set BBPLL reflclk scale to REFCLK /1
SPIWrite 046,03 // Set BBPLL Loop Filter Charge Pump current
SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1
SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1
SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2
SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy
SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy
SPIWrite 043,29 // BBPLL Freq Word (Fractional[7:0])
SPIWrite 042,5C // BBPLL Freq Word (Fractional[15:8])
SPIWrite 041,12 // BBPLL Freq Word (Fractional[23:16])
SPIWrite 044,18 // BBPLL Freq Word (Integer[7:0])
SPIWrite 03F,05 // Start BBPLL Calibration
SPIWrite 03F,01 // Clear BBPLL start calibration bit
SPIWrite 04C,86 // Increase BBPLL KV and phase margin
SPIWrite 04D,01 // Increase BBPLL KV and phase margin
SPIWrite 04D,05 // Increase BBPLL KV and phase margin
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 345.600 us (Done when 0x05E[7]==1)

SPIWrite 是通过SPI写数据，但是 WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock,如何操作？
AD9364按照配置文件写下去就可以配置完了吗，中间过程还要不要操作别的管脚？


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2条回答
ccdzg
2019-07-16 03:03
有相关资料吗？

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