output reg inverse,
output reg sink_valid, // Asserted when data on the data bus is valid.
output reg sink_sop, // start of packet
output reg sink_eop, // end of packet
output [13:0] sink_real,
output [13:0] sink_imag,
output reg [1:0] sink_error, // 指上游模块发生错误
output reg source_ready,
input sink_ready // asserted by fft engine when it can accept data .
/*input [1:0] source_error,
input source_sop,
input source_eop,
input source_valid, // asserted by the fft when there is valid data to output.
// 带符号的块指数:计算FFT计算过程中内部信号值的比例。
*/
);
// reg data_start ;
wire [13:0] q ;
always @ ( posedge clk or negedge reset_n )
begin
if ( !reset_n )
begin
inverse <= 1'b0 ;
sink_valid <= 1'b0 ;
sink_sop <= 1'b0 ;
sink_eop <= 1'b0 ;
sink_error<= 2'b00 ;
source_ready <= 1'b0 ;
state <= IDLE ;
end
else begin
case( state )
IDLE :
begin
if ( sink_ready == 1'b1 )
state <= IN_START ;
else state <= IDLE ;
end
IN_START:
begin
sink_valid <= 1'b1 ;
sink_sop <= 1'b1 ;
// data_start <= 1'b1 ;
i<=0 ;
state <= IN_DATA ;
end
IN_DATA :
begin
sink_sop <= 1'b0 ;
if ( i == 12'd2047 )
begin
state <= IN_END ;
sink_eop <= 1'b1 ;
// data_start <= 1'b0 ;
i <= 1'b0 ;
end
else begin
i = i + 1'b1 ;
state <= IN_DATA ;
end
end
IN_END :
begin
sink_eop <= 1'b0 ;
state <= OUT ;
end
OUT :
begin
if ( i == 12'd5 )
source_ready <= 1'b1 ;
else begin
i <= i + 1 ;
end
end
default : state <= IDLE ;
endcase
end
end
module fft_control(
input clk,
input reset_n,
output reg inverse,
output reg sink_valid, // Asserted when data on the data bus is valid.
output reg sink_sop, // start of packet
output reg sink_eop, // end of packet
output [13:0] sink_real,
output [13:0] sink_imag,
output reg [1:0] sink_error, // 指上游模块发生错误
output reg source_ready,
input sink_ready // asserted by fft engine when it can accept data .
/*input [1:0] source_error,
input source_sop,
input source_eop,
input source_valid, // asserted by the fft when there is valid data to output.
// 带符号的块指数:计算FFT计算过程中内部信号值的比例。
*/
);
// reg data_start ;
wire [13:0] q ;
rom_out dut_rom_out(
.clk(clk) ,
.reset_n (reset_n),
.rden(sink_ready),
.q(q)
)
;
assign sink_real = q ;
assign sink_imag = q ;
reg [12:0] i ;
reg [2:0] state ;
parameter IDLE = 3'd0 ;
parameter IN_START = 3'd1 ;
parameter IN_DATA = 3'd2 ;
parameter IN_END = 3'd3 ;
parameter OUT = 3'd4 ;
always @ ( posedge clk or negedge reset_n )
begin
if ( !reset_n )
begin
inverse <= 1'b0 ;
sink_valid <= 1'b0 ;
sink_sop <= 1'b0 ;
sink_eop <= 1'b0 ;
sink_error<= 2'b00 ;
source_ready <= 1'b0 ;
state <= IDLE ;
end
else begin
case( state )
IDLE :
begin
if ( sink_ready == 1'b1 )
state <= IN_START ;
else state <= IDLE ;
end
IN_START:
begin
sink_valid <= 1'b1 ;
sink_sop <= 1'b1 ;
// data_start <= 1'b1 ;
i<=0 ;
state <= IN_DATA ;
end
IN_DATA :
begin
sink_sop <= 1'b0 ;
if ( i == 12'd2047 )
begin
state <= IN_END ;
sink_eop <= 1'b1 ;
// data_start <= 1'b0 ;
i <= 1'b0 ;
end
else begin
i = i + 1'b1 ;
state <= IN_DATA ;
end
end
IN_END :
begin
sink_eop <= 1'b0 ;
state <= OUT ;
end
OUT :
begin
if ( i == 12'd5 )
source_ready <= 1'b1 ;
else begin
i <= i + 1 ;
end
end
default : state <= IDLE ;
endcase
end
end
endmodule
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