module jishuqi(clk_1khz,reset,pause,MH,ML,SH,SL,MSH,MSL);//计数模块
input clk_1khz,reset,pause;
output reg [3:0]MH;
output reg [3:0]ML;
output reg [3:0]SL;
output reg [3:0]SH;
output reg [3:0]MSL;
output reg [3:0]MSH;
reg clk_100hz_r;
reg [2:0]cnt_clk;
reg cnt_ms;//MSÏòS½øλ
reg cnt_s;//SÏòM½øλ
always@(posedge clk_1khz or negedge reset)
begin
if(!reset)
begin
cnt_clk<=1'b0;
clk_100hz_r<=1'b0;
end
else
begin
if(cnt_clk<=3'd5)
begin
cnt_clk<=1'b0;
clk_100hz_r<=~clk_100hz_r;
end
else
cnt_clk<=cnt_clk+1'b1;
end
end
always@(posedge clk_100hz_r or negedge reset)
begin
if(!reset)
begin
MSL<=4'd0;
MSH<=4'd0;
cnt_ms<=1'b0;
end
else
begin
if(!pause)
begin
if(MSL==9)
begin
MSL<=4'd0;
if(MSH==9)
begin
MSH<=4'd0;
cnt_ms<=1'b1;
end
else
begin
MSH<=MSH+1'b1;
cnt_ms<=1'b0;
end
end
else
begin
MSL<=MSL+1'b1;
cnt_ms<=1'b0;
end
end
end
end
always@(posedge cnt_ms or negedge reset)
begin
if(!reset)
begin
SL<=4'd0;
SH<=4'd0;
cnt_s<=1'b0;
end
else
begin
if(!pause)
begin
if(SL==9)
begin
SL<=4'd0;
if(SH==5)
begin
cnt_s<=1'b1;
SH<=4'd0;
end
else
begin
cnt_s<=1'b0;
SH<=SH+1'b1;
end
end
else
begin
SL<=SL+1'b1;
cnt_s<=1'b0;
end
end
end
end
always@(posedge cnt_s or negedge reset)
begin
if(!reset)
begin
ML<=4'd0;
MH<=4'd0;
end
else
begin
if(!pause)
begin
if(ML==9)
begin
ML<=4'd0;
if(MH==5)
begin
MH<=4'd0;
end
else
MH<=MH+1'b1;
end
else
begin
ML<=ML+1'b1;
end
end
end
end
endmodule
...........................................................................................................................................................................................
module segscan(clk_1khz,reset,MSL,MSH,SL,SH,ML,MH,sel,data,dp);
input clk_1khz,reset;
input [3:0]MSL;//??????
input [3:0]MSH;//??????
input [3:0]SL;//???
input [3:0]SH;//???
input [3:0]ML;//???
input [3:0]MH;//???
output reg [3:0]data;//?????????????
output reg [5:0]sel;//????
output reg dp;
reg [2:0]cnt;
reg [3:0]MSL_reg;
reg [3:0]MSL_r;
reg [3:0]MSH_reg;
reg [3:0]MSH_r;
reg [3:0]SL_reg;
reg [3:0]SL_r;
reg [3:0]SH_reg;
reg [3:0]SH_r;
reg [3:0]ML_reg;
reg [3:0]ML_r;
reg [3:0]MH_reg;
reg [3:0]MH_r;
always@(posedge clk_1khz or negedge reset)
begin
if(!reset)
begin
MSL_r<=4'd0;
MSH_r<=4'd0;
SL_r<=4'd0;
SH_r<=4'd0;
ML_r<=4'd0;
MH_r<=4'd0;
end
else
begin
MSL_r<=MSL;
MSH_r<=MSH;
SL_r<=SL;
SH_r<=SH;
ML_r<=ML;
MH_r<=MH;
MSL_reg<=MSL_r;
MSH_reg<=MSH_r;
SL_reg<=SL_r;
SH_reg<=SH_r;
ML_reg<=ML_r;
MH_reg<=MH_r;
end
end
always@(posedge clk_1khz or negedge reset)
begin
if(!reset)
cnt<=4'd0;
else
cnt<=cnt+1'b1;
end
always@(posedge clk_1khz)
begin
case(cnt)
3'b000:sel<=6'b111111;
3'b001:sel<=6'b011111;
3'b010:sel<=6'b101111;
3'b011:sel<=6'b110111;
3'b100:sel<=6'b111011;
3'b101:sel<=6'b111101;
3'b111:sel<=6'b111110;
default:sel<=6'b111111;
endcase
end
always@(posedge clk_1khz)
begin
case(sel)
6'b111110:begin dp<=1'b1;end
6'b111101:begin dp<=1'b1;end
6'b111011:begin dp<=1'b1;end
6'b110111:begin dp<=1'b0;end
6'b101111:begin dp<=1'b1;end
6'b011111:begin dp<=1'b1;end
default:begin dp<=1'b1;end
endcase
end
always@(posedge clk_1khz)
begin
case(sel)
3'b111:begin data<=MH_reg;end
3'b101:begin data<=ML_reg;end
3'b100:begin data<=SH_reg;end
3'b011:begin data<=SL_reg;end
3'b010:begin data<=MSH_reg;end
3'b001:begin data<=MSL_reg;end
3'b000:begin data<=4'd0;end
default:begin data<=4'd0;end
endcase
end
endmodule
........................................................................................................................................................................................
补充内容 (2017-11-21 20:19):
module shuzipaobiao_top (clk_in,rst,sw_onoff,sel,decout,dp);
input clk_in,rst,sw_onoff;
output wire[6:0]decout;//7位段选数码管
output wire[5:0]sel;//位选
output wire dp;
paobiao_fenpin fp(.clk_in(clk_in),.rst(rst),.clk_1khz(clk_1khz));
xiaodou xiao(.clk_1khz(clk_1khz),.rst(rst),.sw_onoff(sw_onoff),.reset(reset),.on_off(on_off));
jishuqi jishu(.clk_1khz(clk_1khz),.reset(reset),.pause(pause),.MH(MH),.ML(ML),.SH(SH),.SL(SL),.MSH(MSH),.MSL(MSL));
control_cnt cntrol(.clk_1khz(clk_1khz),.reset(reset),.on_off(on_off),.pause(pause));
segscan scan_tb(.clk_1khz(clk_1khz),.reset(reset),.MH(MH),.ML(ML),.SH(SH),.SL(SL),.MSH(MSH),.MSL(MSL),.sel(sel),.dp(dp),.data(data));
顶层模块:
decode4_7 decode(.clk_1khz(clk_1khz),.reset(reset),.data(data),.decout(decout));
endmodule
rtl图的计数模块输出这几个信号到扫描模块 没问题呀 线都连上了
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