上面是数字跑表计数器模块
仿真图,分十位MH计时到5后仍然继续计数,请大神指点这个问题怎么解决。
下面是程序:
module jishuqi(clk_100hz,reset,pause,MH,ML,SH,SL,MSH,MSL);
input clk_100hz,reset,pause;
output reg [3:0]MH;
output reg [3:0]ML;
output reg [3:0]SL;
output reg [3:0]SH;
output reg [3:0]MSL;
output reg [3:0]MSH;
reg cnt_ms;
reg cnt_s;
always@(posedge clk_100hz or negedge reset)
begin
if(!reset)
begin
MSL<=4'd0;
MSH<=4'd0;
cnt_ms<=1'b0;
end
else
begin
if(!pause)
begin
if(MSL==9)
begin
if(MSH==9)
begin
MSL<=4'd0;
MSH<=4'd0;
cnt_ms<=1'b1;
end
else
begin
MSL<=0;
MSH<=MSH+1'b1;
cnt_ms<=1'b0;
end
end
else
begin
MSL<=MSL+1'b1;
cnt_ms<=1'b0;
end
end
end
end
always@(posedge cnt_ms or negedge reset)
begin
if(!reset)
begin
SL<=4'd0;
SH<=4'd0;
cnt_s<=1'b0;
end
else
begin
if(!pause)
begin
if(SL==9)
begin
if(SH==5)
begin
cnt_s<=1'b1;
SH<=4'd0;
SL<=4'd0;
end
else
begin
cnt_s<=1'b0;
SH<=SH+1'b1;
SL<=4'd0;
end
end
else
begin
SL<=SL+1'b1;
cnt_s<=1'b0;
end
end
end
end
always@(posedge cnt_s or negedge reset)
begin
if(!reset)
begin
ML<=4'd0;
MH<=4'd0;
end
else
begin
if(!pause)
begin
if(ML==9)
begin
if(MH==5)
begin
MH<=4'd0;
ML<=4'd0;
end
else
ML<=4'd0;
MH<=MH+1'b1;
end
else
begin
ML<=ML+1'b1;
end
end
end
end
endmodule
功能仿真就出现了这个问题,还没考虑延时
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