verilog状态机问题-szldsj的回答

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szldsj

2019-07-16 16:38

黑桃ACE 发表于 2017-10-8 19:51
你把代码贴上来才知道具体的原因

module fft_control(clk,rst,/*re_fifo,*/wr_fifo,rst_fifo,w_cycle,wr_full1,wr_full2,wr_fifo1,wr_fifo2,fftpts_in,sink_eop,sink_sop,sink_valid,start_16,fft16_over,switch,re_im,out_reim,count_in,recycle,re1,re2);
input clk,rst;
input wr_fifo,wr_full1,start_16,fft16_over,wr_full2;
input [47:0] re_im;
output [10:0] fftpts_in;
output /*re_fifo,*/sink_eop,sink_sop,sink_valid;
output rst_fifo,re1,re2;
output w_cycle,switch,wr_fifo1,wr_fifo2;
output [13:0] count_in;
output [47:0] out_reim;
output[4:0] recycle;
wire [47:0] out_reim;
reg pd;
reg w_cycle;
reg re_fifo;
reg rst_fifo;
reg [3:0] state1;
reg [4:0] recycle; //修改，加入周期计数，积累16周期
reg [4:0] cnt;//存储计数
reg [10:0] fftpts_in;
reg [13:0] count_in;
reg sink_eop,sink_sop;
reg sink_valid;
reg flag;
assign out_reim=flag? re_im:48'd0;
assign re1=pd? re_fifo:1'b0;
assign re2=pd? 1'b0:re_fifo;
assign wr_fifo2=pd? wr_fifo:1'b0;
assign wr_fifo1=pd? 1'b0:wr_fifo;
always @(posedge clk)
if(!rst) begin
re_fifo<=1'b0;
state1<=4'b0000;
rst_fifo<=1'b1;
w_cycle<=1'b0;
recycle<=5'd0;//周期计数
fftpts_in<=11'd1024;
sink_eop<=1'b0;
sink_sop<=1'b0;
sink_valid<=1'b0;
count_in<=12'd0;
flag<=1'b1;
pd<=1'b0;
cnt<=5'd0;
end
else
case(state1)
4'b0000: begin
rst_fifo<=1'b0; //1024点FFT变换阶段
flag<=1'b1; //16 dian bianhuan qiehuan biaozhiwei
count_in<=14'd0; //jisu
re_fifo<=1'b0; //ad shuju duqu fifo shineng
w_cycle<=1'b0;
//zhouqi biaozhiwei
recycle<=5'd0;//周期计数
sink_eop<=1'b0; //FFT shuju shuru qishibiaozhi
sink_sop<=1'b0; //FFT shuru jieshu biaozhi
sink_valid<=1'b0; //shuju shuruyouxiao biaozhiwei
fftpts_in<=11'd1024; //fft shuruchangdu
if(((wr_full1||wr_full2)==1'b1)&&(wr_fifo==1'b0)) begin //dang fifo duman 2048 wr_full==1'b1,qie wr_fifo==1'b0;
if(cnt<=5'd16) begin
state1<=4'b0001; //zhuanru xia yige zhuangtai
re_fifo<=1'b1; //dushineng
count_in<=10'd0;
cnt<=5'd0;
end
else begin
state1<=4'b0001; //zhuanru xia yige zhuangtai
re_fifo<=1'b1; //dushineng
count_in<=10'd0;
cnt<=cnt+1'b1;
pd<=~pd;
end
end
else begin
state1<=4'b0000;
end
end
4'b0001: begin
sink_valid<=1'b1; //数据输入有效标志
sink_sop<=1'b1; //输入数据流起始标志
sink_eop<=1'b0; //输入数据流结束标志
state1<=4'b0010; //转入下一状态，数据开始输入
count_in<=count_in+1'b1; //开始计第一点数据
end
4'b0010: begin
if(count_in==14'd2047) begin //1024dianFFT
if(recycle==5'd15) // 增加周期判断
begin
sink_eop<=1'b1; //shujukuai jieshu biaozhi
count_in<=14'd0;
w_cycle<=1'b1;
state1<=4'b0011; //zhuanru 16dian bianhuan
end
else
begin
recycle=recycle+1;
sink_eop<=1'b1;
count_in<=10'd0;
w_cycle<=1'b1;
state1<=4'b0000;
end
end
else
if(count_in==14'd1023) begin //shang shaopin
sink_eop<=1'b1; //shangshaopin shuju shuru jieshu
state1<=4'b0001; //fanhui shang yi ge zhuangtai wanchengxiashaopinshuju shuru
count_in<=count_in+1'b1;
end
else
count_in<=count_in+1'b1;
sink_sop<=1'b0;
end
//16dian FFT bianhuan jieduan
4'b0011: begin
re_fifo<=1'b0;
fftpts_in<=11'd16; //停止从fifo中读取数据
sink_eop<=1'b0; //shuju jiesubiaozhi zhi 0
sink_valid<=1'b0;
w_cycle<=1'b0;
count_in<=10'd0;
if(start_16)begin
state1<=4'b0100; //16点变换开始
end
else begin
state1<=4'b0011;
end
end
4'b0100: begin
sink_valid<=1'b1; //16dianbianhuan shujushuruzhunbeijieduan
sink_sop<=1'b1;
sink_eop<=1'b0;
state1<=4'b0101;
end
4'b0101: begin
if(count_in==14'd15) begin //16dianshuju shifou shuruwanbi
sink_eop<=1'b1;
count_in<=12'd0;
if(fft16_over) //16zhouqi shuju chuliwanbi
state1<=4'b0000; //chongxinkaishixiayilunshuju shuru
else
state1<=4'b0110; //ruguomeijieshu jixuxiayige16dianbianhuan
end
else begin
count_in<=count_in+1'b1;
flag<=1'b1; //biaozhiwei zhi wei 1
end
sink_sop<=1'b0;
end
4'b0110: begin
sink_eop<=1'b0;
sink_sop<=1'b1;
//sink_valid<=1'b0;
state1<=4'b0101;
flag<=1'b1;
end
default: state1<=state1;
endcase
reg switch;
always @(posedge clk)
if(!rst)
switch<=1'b1;
else
case(fftpts_in)
11'd512: switch<=1'b1;
11'd16: switch<=1'b0;
default: switch<=switch;
endcase
endmodule
//先输入单个周期的1024点个数据然后进行周期计算，即录入16个单周期采样数据，设置快速傅里叶变换标志，即进行16点快速变换，或1024点快速变换

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