FPGA

时序仿真出现高阻态

2019-07-15 21:31发布

站内问答 / FPGA
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在做时序仿真的时候，发现一个问题,代码如下：assign gateway_out1 = gateway_in10 * gateway_in11
结果发现 输出带有高阻态,波形如图。
在做功能仿真的时候没有问题，做时序仿真就出现问题了。 请问这是什麼原因造成的。

mult_WRONG.PNG

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10条回答
344214187
2019-07-16 00:52
warning
The signal InvKineticModule/Position/topmult_position/mult_mcw_17Q7/out<1> has no load.  PAR will not attempt to route
   this signal.
WARNING:Par:288 - The signal InvKineticModule/Position/topmult_position/mult_mcw_17Q7/out<2> has no load.  PAR will not attempt to route
   this signal.
WARNING:Par:288 - The signal InvKineticModule/Position/topmult_position/mult_mcw_17Q7/out<3> has no load.  PAR will not attempt to route
   this signal.
WARNING:Par:288 - The signal InvKineticModule/Position/topmult_position/mult_mcw_17Q7/out<4> has no load.  PAR will not attempt to route
   this signal.
WARNING:Par:288 - The signal InvKineticModule/Position/topmult_position/mult_mcw_17Q7/out<5> has no load.  PAR will not attempt to route
   this signal.
WARNING:Par:288 - The signal InvKineticModule/Position/topmult_position/mult_mcw_17Q7/out<6> has no load.  PAR will not attempt to route
   this signal.

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