vivado中synthesis通过，implement通过，但是在编译simula
tion的时候报错：
[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Administrator/Desktop/shuma/shumaxianshi/shumaxianshi.sim/sim_1/behav/xvlog.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
语言为verilog
这个问题怎么解决哇
哭死了要
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