library ieee;
use ieee.std_logic_1164.all;
en
tity first is
port(x:in std_logic_vector(1 downto 0);
y:out std_logic_vector(1 downto 0));
end first;
architecture behave of first is
begin
y(1)<=x(1);
y(0)<=x(0);
end behave;
刚下载的9.0,前边都没错,也没警告,到了
仿真就出错了。
64位的如何破解, 按教程破解了好多次,也不行
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