module flash_control(clk,reset,flash_q,wr,addr_wrf,data_wrf,rd,addr_rdf,
flash_c,flash_w,flash_h,flash_s,flash_d,fs,dataout,req_data,state);
input clk;
input reset;
input flash_q;
input wr; //往flash写数据的使能,上升沿有效
input [23:0] addr_wrf; //写flash的首地址
input [15:0] data_wrf; //写flash的数据,延迟req_data一个时钟
input rd; //从flash读数据的使能,上升沿有效
input [23:0] addr_rdf; //读flash的首地址,此程序一次读2048个数据,可自行更改
output flash_c;
output flash_w;
output flash_h;
output reg flash_s;
output reg flash_d;
output reg fs; //读使能rd给过后从flash读出的真实数据帧信号
output reg [15:0] dataout; //读使能rd给过后从flash读出的真实数据,与fs对齐
output reg req_data; //flash擦除完毕需要给flash数据,req_data为写数据请求信号,提前data_wrf一个时钟
output [5:0] state;
reg [5:0] state=6'b00000;
reg aux_wr;
reg aux_rd;
reg wip;
reg [23:0] i;
reg [3:0] j1;
reg [3:0] j2;
reg [3:0] j3;
reg [3:0] k;
reg [1:0] state_addr;
reg [7:0] addr_H;
reg [7:0] addr_M;
reg [7:0] addr_L;
reg [23:0] addr_se;
reg [23:0] addr_pp;
reg [7:0] read_q;
reg [23:0] addr_rd;
reg fs1;
reg fs2;
reg [15:0] dataout1;
reg [15:0] dataout2;
reg [3:0] count_q;
reg [23:0] r;
assign flash_c = clk;
assign flash_w = 1'b1;
assign flash_h = 1'b1;
parameter p_wren =8'b0000_0110,
p_rdsr =8'b0000_0101,
p_pp =8'b0000_0010,
p_ce =8'b0110_0000,
p_be =8'b1101_1000,
p_read_q=8'b0000_0011;
always@(posedge clk)
begin
aux_wr <= wr;
aux_rd <= rd;
if(!reset) begin
i <= 0;
j1 <= 0;
j2 <= 0;
j3 <= 0;
k <= 0;
flash_s <= 0;
addr_se <= addr_wrf;
addr_pp <= addr_wrf;
read_q <= p_read_q;
fs1 <= 0;
dataout1 <= 0;
dataout2 <= 0;
req_data <= 0;
state <= 0;
end
else begin
case(state)
0:begin
i <= 0;
j1 <= 0;
j2 <= 0;
j3 <= 0;
k <= 0;
flash_s <= 1;
addr_se <= addr_wrf;
addr_pp <= addr_wrf;
addr_rd <= addr_rdf;
state_addr <= 0;
read_q <= p_read_q;
fs1 <= 0;
dataout1 <= 0;
dataout2 <= 0;
req_data <= 0;
if(wr==1 && aux_wr==0) begin
state <= 1;
end
else if(rd==1 && aux_rd==0) begin
state <= 17;
end
end
1:begin
flash_s <= 0;
addr_H[7:0]<=addr_se[23:16];
addr_M[7:0]<=addr_se[15:8];
addr_L[7:0]<=addr_se[7:0];
if(i<7) begin
i <= i+1;
flash_d <= p_wren[7-i]; //0000_0110
end
else begin
i <= 0;
flash_d <= p_wren[0];
state <= 2;
end
end
2:begin
flash_s <= 1;
if(i<7) begin
i <= i+1;
end
else begin
i <= 0;
state <= 3;
end
end
3:begin
flash_s <= 0;
if(i<7) begin
i <= i+1;
flash_d <= p_be[7-i]; //1101_1000
end
else begin
i <= 0;
flash_d <= p_be[0];
state <= 4;
end
end
4:begin
case (state_addr)
0:begin
if(j1<7) begin
j1 <= j1+1;
flash_d <= addr_H[7-j1];
end
else begin
j1 <= 0;
flash_d <= addr_H[0];
state_addr <= 1;
end
end
1:begin
if(j2<7) begin
j2 <= j2+1;
flash_d <= addr_M[7-j2];
end
else begin
j2 <= 0;
flash_d <= addr_M[0];
state_addr <= 2;
end
end
2:begin
if(j3<7) begin
j3 <= j3+1;
flash_d <= addr_L[7-j3];
end
else begin
j3 <= 0;
flash_d <= addr_L[0];
state<= 5;
end
end
default:begin end
endcase
end
5:begin
flash_s <= 1;
state_addr <= 0;
j1 <= 0;
j2 <= 0;
j3 <= 0;
wip <= 0;
if(i<7) begin
i <= i+1;
end
else begin
i <= 0;
state <= 6;
end
end
6:begin
flash_s <= 0;
if(i<7) begin
i <= i+1;
flash_d <= p_rdsr[7-i]; //0000_0101
end
else begin
i <= 0;
flash_d <= p_rdsr[0];
state <= 7;
end
end
7:begin
flash_s <= 0;
if(i==8) begin
i <= 0;
wip <= flash_q;
state <= 8;
end
else begin
i <= i+1;
end
end
8:begin
flash_s <= 0;
if(wip) begin
i <= i+1;
state <= 8;
if(i==7) begin
i <= 0;
wip <= flash_q;
end
end
else begin
state <= 9;
end
end
9:begin
flash_s <= 1;
if(i<15) begin
i <= i+1;
end
else begin
i <= 0;
state <= 10;
end
end
10:begin
flash_s <= 0;
if(i<7) begin
i <= i+1;
flash_d <= p_wren[7-i]; //0000_0110
end
else begin
i <= 0;
flash_d <= p_wren[0];
state <= 11;
end
end
11:begin
flash_s <= 1;
if(i<7) begin
i <= i+1;
end
else begin
i <= 0;
state <= 12;
end
end
12:begin
flash_s <= 0;
addr_H[7:0] <= addr_pp[23:16];
addr_M[7:0] <= addr_pp[15:8];
addr_L[7:0] <= addr_pp[7:0];
if(i<7) begin
i <= i+1;
flash_d <= p_pp[7-i]; //0000 0010
end
else begin
i <= 0;
flash_d <= p_pp[0];
state <= 13;
end
end
13:begin
flash_s <= 0;
case (state_addr)
0:begin
if(j1<7) begin
j1 <= j1+1;
flash_d <= addr_H[7-j1];
end
else begin
j1 <= 0;
flash_d <= addr_H[0];
state_addr <= 1;
end
end
1:begin
if(j2<7) begin
j2 <= j2+1;
flash_d <= addr_M[7-j2];
end
else begin
j2 <= 0;
flash_d <= addr_M[0];
state_addr <= 2;
end
end
2:begin
if(j3<7) begin
j3 <= j3+1;
flash_d <= addr_L[7-j3];
if(j3==4) begin
req_data <= 1;
end
end
else begin
j3 <= 0;
flash_d <= addr_L[0];
//req_data <= 1;
state <= 14;
end
end
default:begin end
endcase
end
14:begin
flash_s <= 0;
state_addr <= 0;
j1 <= 0;
j2 <= 0;
j3 <= 0;
if(i<2047) begin
i <= i+1;
if(k<15) begin
k <= k+1;
flash_d <= data_wrf[15-i];
end
else begin
k <= 0;
flash_d <= data_wrf[0];
end
end
else begin
req_data <= 0;
i <= 0;
flash_d <= data_wrf[0];
state <= 0;
end
end
17:begin
flash_s <= 1;
addr_H[7:0] <= addr_rd[23:16];
addr_M[7:0] <= addr_rd[15:8];
addr_L[7:0] <= addr_rd[7:0];
state_addr <= 0;
read_q <= p_read_q;
i <= 0;
j1 <= 0;
j2 <= 0;
j3 <= 0;
count_q <= 0;
fs1 <= 0;
dataout1 <= 0;
dataout2 <= 0;
state <= 18;
end
18:begin
flash_s <= 0;
if(i<7) begin
i <= i+1;
flash_d <= read_q[7-i];
end
else begin
i <= 0;
flash_d <= read_q[0];
state <= 19;
end
end
19:begin
case (state_addr)
0:begin
if(j1<7) begin
j1 <= j1+1;
flash_d <= addr_H[7-j1];
end
else begin
j1 <= 0;
flash_d <= addr_H[0];
state_addr <= 1;
end
end
1:begin
if(j2<7) begin
j2 <= j2+1;
flash_d <= addr_M[7-j2];
end
else begin
j2 <= 0;
flash_d <= addr_M[0];
state_addr <= 2;
end
end
2:begin
if(j3<7) begin
j3 <= j3+1;
flash_d <= addr_L[7-j3];
end
else begin
j3 <= 0;
flash_d <= addr_L[0];
state <= 20;
end
end
default:begin end
endcase
end
20:begin
if(r<=2048) begin
r <= r+1;
dataout1[0] <= flash_q;
dataout1[15:1] <= dataout1[14:0];
count_q <= count_q+1;
if(r>=16 && r<=2048) begin
fs1 <=1;
if(count_q==15) begin
count_q <= 0;
end
else if(count_q==1) begin
dataout2[15:0] <= dataout1[15:0];
end
end
else begin
if(count_q==15) begin
count_q <= 0;
end
else if(count_q==1) begin
dataout2[15:0] <= dataout1[15:0];
end
end
end
else begin
count_q <= 0;
dataout1[0] <= flash_q;
dataout1[15:1] <= dataout1[14:0];
dataout2 <= dataout1;
state <= 21;
end
end
21:begin
flash_s <= 1;
r <= 0;
state_addr <= 0;
if(i<15) begin
i <= i+1;
dataout1 <= flash_q;
dataout1[15:1] <= dataout1[14:0];
end
else begin
i <= 0;
fs1 <= 0;
dataout1 <= 0;
state <= 0;
end
end
default:begin end
endcase
end
end
always@(posedge clk)
begin
fs2 <= fs1;
fs <= fs2;
dataout <= dataout2;
end
endmodule
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