modelsim仿真错误的问题。

2019-07-15 22:11发布

小弟最近在学习quartus ii 的DDR2的ip核,编写了一个程序,在程序中实例化了DDR2的ip和,想用modelsim仿真看看波形,仅仅是功能仿真(RTL仿真),但是仿真出现了很多一样的错误,如下,请问各位大神遇到过这种情况吗?是怎么解决的?

# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter 'CFG_MEM_IF_CS_WIDTH' not found for override.
#
#         Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter 'CFG_RANK_tiMER_OUTPUT_REG' not found for override.
#
#         Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2328): Module parameter 'CFG_RANK_TIMER_OUTPUT_REG' not found for override.
#
#         Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2508): Module parameter 'CFG_CTL_ARBITER_TYPE' not found for override.
#
#         Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
# Loading a0.alt_mem_ddrx_mm_st_converter
# Loading oct0.altera_mem_if_oct_cyclonev
# Loading dll0.altera_mem_if_dll_cyclonev
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./ddr2_ceshi_run_msim_rtl_verilog.do PAUSED at line 214


这个错误在百度上找不到,自己是一点摸不到头脑。小弟先拜谢了!
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