我在网上找了4x4移位累加乘法器的代码,然后想把它变成8x8的,代码如图,其中multi44就是4x4乘法器模块。然后在仿真时提示 Illegal output port connection for "'dout' (3rd connection)".不知道怎么改。。求指点。
顺便,我这样写能实现功能吗,不能仿真我也不知道自己写的对不对。如果不对的话,要怎么扩展呢?
always @ (posedge Clk or negedge Rst_n)
begin
if(!Rst_n)
begin
state <= 4'd0;
count <= 4'd0;
p <= 16'd0;
t <= 8'd0;
y <= 16'd0;
end
else
begin
case(state)
4'd0:
begin
state <= 4'd1;
count <= 8'd0;
p <= {8'd0,x0};
end
4'd1:
begin
if(count >= 8'd8)
state <= 4'd3;
else
begin
if( x1[count] )
begin
state<= 4'd2;
t <= 8'd0;
y <= y + p;
p <= {8'd0,x0};
end
else
state <= 4'd1;
count <= count + 1'b1;
end
end
4'd2:
begin
if(t >= count)
state <= 4'd1;
else
begin
state <= 4'd2;
t <= t + 1'b1;
p <= p<<1;
end
end
4'd3:
begin
//y <= p;
end
endcase
end
end
//always @ (posedge Clk or negedge Rst_n)
//begin
// if(!Rst_n)
// begin
// y <= 16'd0;
// end
// else
// y <= x0*x1;
//end
module mul_ser(
Clk,
Rst_n,
x0,
x1,
y
);
input Clk;
input Rst_n;
input [7:0]x0;
input [7:0]x1;
output reg [15:0]y;
reg [7:0]t;
reg [15:0]p;
reg [7:0]count;
reg [3:0]state;
always @ (posedge Clk or negedge Rst_n)
begin
if(!Rst_n)
begin
state <= 4'd0;
count <= 4'd0;
p <= 16'd0;
t <= 8'd0;
y <= 16'd0;
end
else
begin
case(state)
4'd0:
begin
state <= 4'd1;
count <= 8'd0;
p <= {8'd0,x0};
end
4'd1:
begin
if(count >= 8'd8)
state <= 4'd3;
else
begin
if( x1[count] )
begin
state<= 4'd2;
t <= 8'd0;
y <= y + p;
p <= {8'd0,x0};
end
else
state <= 4'd1;
count <= count + 1'b1;
end
end
4'd2:
begin
if(t >= count)
state <= 4'd1;
else
begin
state <= 4'd2;
t <= t + 1'b1;
p <= p<<1;
end
end
4'd3:
begin
//y <= p;
end
endcase
end
end
//always @ (posedge Clk or negedge Rst_n)
//begin
// if(!Rst_n)
// begin
// y <= 16'd0;
// end
// else
// y <= x0*x1;
//end
endmodule
最佳答案
一周热门 更多>