毕设用SF-CY3的板子做交通灯控制器 现在跑不起来,急求解决,求大神们帮帮,解决者必有重谢

2019-07-15 22:43发布

tica, sans-serif, 宋体">第一个问题:EN使能信号连哪个端口好
第二个问题:SF-CY3外接端口怎么使用
第三个问题:程序是否有问题
这是verilog程序:module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT);
output[7:0] ACOUNT,BCOUNT;
output[3:0] LAMPA,LAMPB;
input CLK,EN;
reg[7:0] numa,numb;
reg tempa,tempb;
reg[2:0] counta,countb;
reg[7:0] ared,ayellow,agreen,aleft,bred,byellow,bgreen,bleft;
reg[3:0] LAMPA,LAMPB;
always @(EN)
if(EN)
begin //设置各种灯的计数器的预置数
ared  <=8'd55;  //55 秒
ayellow <=8'd5; //5 秒
agreen <=8'd40;  //40 秒
aleft  <=8'd5;  //15 秒
bred  <=8'd65;  //65 秒
byellow <=8'd5; //5 秒
bleft  <=8'd5;  //15 秒
bgreen <=8'd30;  //30 秒
end
assign ACOUNT=numa;
assign BCOUNT=numb;
always @(posedge CLK) //该进程控制 A 方向的四种灯
begin
if(EN)
begin
if(!tempa)
begin
tempa<=1;
case(counta) //控制亮灯的顺序
3'b000: begin numa<=agreen; LAMPA<=LAMPA[1]; counta<=3'b001; end
3'b001: begin numa<=ayellow;  LAMPA<=LAMPA[2]; counta<=3'b010; end
3'b010: begin numa<=aleft;  LAMPA<=LAMPA[0]; counta<=3'b011; end
3'b011: begin numa<=ayellow;  LAMPA<=LAMPA[2]; counta<=3'b100; end
3'b100: begin numa<=ared;  LAMPA<=LAMPA[3]; counta<=3'b000; end
default:  LAMPA<=LAMPA[3];
endcase
end
else begin //倒计时
if(numa>1)
if(numa[3:0]==0) begin
numa[3:0]<=4'b1001;
numa[7:4]<=numa[7:4]-1;
end
else numa[3:0]<=numa[3:0]-1;
if (numa==2) tempa<=0;
end
end
else begin
LAMPA<=LAMPA[3];
counta<=0; tempa<=0;
end
end
always @(posedge CLK) //该进程控制 B 方向的四种灯
begin
if (EN)
begin
if(!tempb)
begin
tempb<=1;
case (countb) //控制亮灯的顺序
3'b000: begin numb<=bred;  LAMPB<=LAMPA[3]; countb<=3'b001; end
3'b001: begin numb<=bgreen; LAMPB<=LAMPA[1]; countb<=3'b010; end
3'b010: begin numb<=byellow;  LAMPB<=LAMPA[2]; countb<=3'b011; end
3'b011: begin numb<=bleft;  LAMPB<=LAMPA[0]; countb<=3'b100; end
3'b100: begin numb<=byellow;  LAMPB<=LAMPA[2]; countb<=3'b000; end
default:  LAMPB<=LAMPA[3];
endcase
end
else
begin //倒计时
if(numb>1)
if(numb[3:0]==0) begin
numb[3:0]<=3'b1001;
numb[7:4]<=numb[7:4]-1;
end
else numb[3:0]<=numb[3:0]-1;
if(numb==2) tempb<=0;
end
end
else begin
LAMPB<=LAMPB[3];
tempb<=0; countb<=0;
end
end
endmodule


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