//分频单元
module clock_divder(
    input       sys_rstn,
    input       clk_50M ,
    output  reg clk_50Hz
);

reg [31:0] cnt;

always @(posedge clk_50M or negedge sys_rstn)
    if (!sys_rstn)
        cnt <= 32'd0;
    else if (cnt >= 32'd5)//(cnt >= 32'd499999)
        cnt <= 32'd0;
    else
        cnt <= cnt + 1'b1;

always @(posedge clk_50M or negedge sys_rstn)
    if (!sys_rstn)
        clk_50Hz <= 1'b0;
    else if (cnt >= 32'd5)//(cnt >= 32'd499999)
        clk_50Hz <= ~clk_50Hz;

endmodule