本人新手，按照步骤安装好quartusii11.0和modelsim后，进行到最后一步modelsim仿真时出现问题。就像这样，是在调用ROM模块进行仿真的时候出现的问题，程序按视频教程走的，作者用的10.1可以直接调用及仿真。已经弄了一天了，不知道是软件破解问题还是modelsim的调用问题，不知道该从什么方面下手了，拿 出所有积分跪求各位大神指引迷津。                          file:///C:UsersHZHAppDataRoamingTencentUsers1821814774QQWinTempRichOle$O`MPE0_5}~F(~J{82`A23S.png
程序调用MIF文件前是这样的
`timescale 1ns/1ns

`define clk_period 20

module sin_bb;
reg[5:0]addr;
reg clk;

wire[7:0]q;


  sin sin (
        .address(addr),
        .clock(clk),
        .q(q));

   initial clk=1;
        always #(`clk_period/2) clk=~clk;
        integer i;
       
        initial begin
           addr=0;
                for(i=0;i<63;i=i+1)begin
                #`clk_period;
                addr=addr+1;
                end
                #(`clk_period* 50);
                $stop;
        end
endmodule



程序在调用mif文件后是这样的
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.all;

ENTITY sin IS
        PORT
        (
                address                : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                clock                : IN STD_LOGIC  := '1';
                q                : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
END sin;


ARCHITECTURE SYN OF sin IS

        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (7 DOWNTO 0);



        COMPONENT altsyncram
        GENERIC (
                clock_enable_input_a                : STRING;
                clock_enable_output_a                : STRING;
                init_file                : STRING;
                intended_device_family                : STRING;
                lpm_hint                : STRING;
                lpm_type                : STRING;
                numwords_a                : NATURAL;
                operation_mode                : STRING;
                outdata_aclr_a                : STRING;
                outdata_reg_a                : STRING;
                widthad_a                : NATURAL;
                width_a                : NATURAL;
                width_byteena_a                : NATURAL
        );
        PORT (
                        address_a        : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                        clock0        : IN STD_LOGIC ;
                        q_a        : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
        END COMPONENT;

BEGIN
        q    <= sub_wire0(7 DOWNTO 0);

        altsyncram_component : altsyncram
        GENERIC MAP (
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => "sin.mif",
                intended_device_family => "Cyclone II",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 64,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "CLOCK0",
                widthad_a => 6,
                width_a => 8,
                width_byteena_a => 1
        )
        PORT MAP (
                address_a => address,
                clock0 => clock,
                q_a => sub_wire0
        );



END SYN;
错误是这样的
Error: Text Design File syntax error: Text Design File contains END where '(', IF, a symbolic name, or a number was expected
Error: Text Design File syntax error: Text Design File contains BEGIN where END was expected
Error: Text Design File syntax error: Text Design File contains END where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains END where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains END where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains IF where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains IF where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains END where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains END where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains END where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains END where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected
Error: Text Design File syntax error: Text Design File contains IF where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected

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