为什么没有波形呢 怎么改,求指教?着急
被测模块:
module PLL_count(dnup,enable,borrow,kmode,carry,rst,kclk);
input dnup;//Óë¼øÏàÆ÷µÄseÏàÁ¬
input rst;
input [2:0]kmode;
input enable;
input kclk;
output wire borrow;
output wire carry;
reg [8:0]count;
reg [8:0]ktop;
always@(count)
begin
case(kmode)
3'b001: ktop<=7;
3'b010: ktop<=15;
3'b011: ktop<=31;
3'b100: ktop<=63;
3'b101: ktop<=127;
3'b110: ktop<=255;
3'b111: ktop<=311;
default:ktop<=15;
endcase
end
always@(posedge kclk or negedge rst)
begin
if(!rst)
count<=0;
else if(enable)
begin
if(!dnup)
begin
if(count==ktop)
count<=0;
else
count<=count+1;
end
else
begin
if(count==0)
count<=ktop;
else
count<=count-1;
end
end
end
assign carry=enable&(!dnup)&(count==ktop);
assign borrow=enable&dnup&(count==0);
endmodule
测试模块:
`
timescale 1ns/ 100ps
module PLL_count_test;
reg kclk,rst,dnup,enable;
reg [2:0]kmode;
wire borrow;
wire carry;
wire [8:0]kstop;
parameter TIME_PERIOD=2;
PLL_count counter_test(.kclk(kclk),.rst(rst),.dnup(dnup),
.enable(enable),.kmode(kmode),.borrow(borrow),.carry(carry));
always
begin
#2 kclk=~kclk;
end
initial
begin
rst=0;
enable=0;
kclk=0;
kmode=4;
dnup=0;
end
always@(posedge kclk)
begin
#2 rst=1;
#4 enable=1;
#5 dnup=1;
#5 enable=2;
#5 kmode=3;
#1000000 $finish;
end
always
begin
$display($time,"rst=%b,kclk=%b,enable=%b,kmode=%b,dnup=%b,borrow=%b,carry=%b,kstop=%d",rst,kclk,enable,kmode,dnup,borrow,carry,kstop);
end
endmodule
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