FPGA

fpga控制ad采集数据把波形和幅值显示在lcd屏幕上

2019-07-15 23:01发布

站内问答 / FPGA
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tica, sans-serif, 宋体">显示波形的代码如下：已经可以显示波形，求显示幅值大小的代码该怎么加？加在哪里？`timescale 1ns / 1ps

module lcd_driver(
clk,rst_n,
lcd_clk,lcd_de,lcd_r,lcd_g,lcd_b,
lcd_en,
lcd_rfdb,lcd_rfreq,lcd_rfclr,
lcd_dhq,lcd_djreq,
mcu_ledon,
wave_rden,wave_datbus,
wave_xs,wave_ys,wave_xe,wave_ye,wave_fcor,wave_bcor,wave_disp
);
//系统信号
input clk; //液晶驱动时钟，通常和液晶说明书一致的频率
input rst_n; //低电平复位
//LCD接口
output lcd_clk;
output lcd_de; //display data enable signal
output[4:0] lcd_r; //display red data
output[5:0] lcd_g; //display green data
output[4:0] lcd_b; //display blue data
//LCD背光控制接口
output lcd_en; //backlight enable
//SDRAM数据流接口（显示层）
input[15:0] lcd_rfdb; //输出到LCD模块待显示的SDRAM读出数据
output lcd_rfreq; //LCD模块发出的读FIFO请求信号，高电平有效
output lcd_rfclr; //LCD模块发出的读FIFO复位，低电平有效
//SDRAM数据流接口（叠加层）
input[15:0] lcd_dhq; //输出到LCD模块待显示的叠加层SDRAM读出数据
output lcd_djreq; //LCD模块发出的叠加层读FIFO请求信号，高电平有效
//LCD背光控制
input mcu_ledon; //NIOS2控制背光:1--开背光，0--关背光
//LCD读波形坐标数据接口
output wave_rden; //双口RAM读使能信号
input[7:0] wave_datbus; //读当前波形高度数据
//wave产生控制寄存器
input[9:0] wave_xs,wave_ys; //波形显示起始位置
input[9:0] wave_xe,wave_ye; //波形显示结束位置
input[15:0] wave_fcor,wave_bcor; //波形显示前/背景 {MOD}
input wave_disp; //波形显示使能信号，高电平有效

//-----------------------------------------------------------
//VGA Timing 800*480 & 33MHz & 60Hz

parameter VGA_HTT = 12'd1056-12'd1; //Hor Total Time
parameter VGA_HST = 12'd0; //Hor Sync  Time
parameter VGA_HBP = 12'd46; //Hor Back Porch
parameter VGA_HVT = 12'd800; //Hor Valid Time
parameter VGA_HFP = 12'd210; //Hor Front Porch

parameter VGA_VTT = 12'd525-12'd1; //Ver Total Time
parameter VGA_VST = 12'd0; //Ver Sync Time
parameter VGA_VBP = 12'd23; //Ver Back Porch
parameter VGA_VVT = 12'd480; //Ver Valid Time
parameter VGA_VFP = 12'd22; //Ver Front Porch

parameter VGA_CORBER = 12'd100; //8等分做Color bar显示

//-----------------------------------------------------------
//x and y counter
reg[11:0] xcnt;
reg[11:0] ycnt;

always @(posedge clk or negedge rst_n)
if(!rst_n) xcnt <= 12'd0;
else if(xcnt >= VGA_HTT) xcnt <= 12'd0;
else xcnt <= xcnt+1'b1;

always @(posedge clk or negedge rst_n)
if(!rst_n) ycnt <= 12'd0;
else if(xcnt == VGA_HTT) begin
if(ycnt >= VGA_VTT) ycnt <= 12'd0;
else ycnt <= ycnt+1'b1;
end
else ;

//-----------------------------------------------------------
//vga valid signal generate
reg vga_valid;

wire yvalid = (ycnt >= (VGA_VST+VGA_VBP)) && (ycnt < (VGA_VST+VGA_VBP+VGA_VVT));

always @(posedge clk or negedge rst_n)
if(!rst_n) vga_valid <= 1'b0;
else if(yvalid &&(xcnt >= (VGA_HST+VGA_HBP)) && (xcnt < (VGA_HST+VGA_HBP+VGA_HVT)))
vga_valid <= 1'b1;
else vga_valid <= 1'b0;

assign lcd_de = vga_valid;

//-----------------------------------------------------------
//SDRAM读控制信号产生逻辑

//LCD新的一屏指示信号，低电平有效，用于SDRAM读FIFO数据清空
assign lcd_rfclr = (ycnt == VGA_VTT);

//SDRAM读显示数据请求信号产生
reg lcd_dbdjreqr;

//提前2个时钟周期读数据。第0时钟读数据；第1时钟出数据，此时对读出数据做处理；第2时钟数据送显示
always @(posedge clk or negedge rst_n)
if(!rst_n) lcd_dbdjreqr <= 1'b0;
else if(yvalid && (xcnt >= (VGA_HST+VGA_HBP-4)) && (xcnt < (VGA_HST+VGA_HBP+VGA_HVT-4))) lcd_dbdjreqr <= 1'b1;
else lcd_dbdjreqr <= 1'b0;

assign lcd_djreq = lcd_dbdjreqr; //LCD模块发出的叠加层读FIFO请求信号，高电平有效（若当前显示模式控制寄存器为0，则只显示当前显示页。不产生叠加页读请求）

reg lcd_dbrfreqr;

always @(posedge clk or negedge rst_n)
if(!rst_n) lcd_dbrfreqr <= 1'b0;
else lcd_dbrfreqr <= lcd_dbdjreqr;

assign lcd_rfreq = lcd_dbrfreqr; //LCD模块发出的读FIFO请求信号，高电平有效

////////////////////////////////////////////////////////////////////////////////
//波形界面产生控制逻辑
////////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------
//wire[11:0] x_dis = xcnt-(VGA_HST+VGA_HBP)-2;
//wire[11:0] y_dis = ycnt-(VGA_VST+VGA_VBP)-2;

//assign wave_rden = (x_dis >= {2'd0,wave_xs}) & (x_dis <= {2'd0,wave_xe}); //双口RAM读使能信号
reg wave_rden; //双口RAM读使能信号

always @(posedge clk or negedge rst_n)
if(!rst_n) wave_rden <= 1'b0;
else if((xcnt >= {2'd0,wave_xs}+(VGA_HST+VGA_HBP-5)) && (xcnt < {2'd0,wave_xe}+(VGA_HST+VGA_HBP-5))) wave_rden <= 1'b1;
else wave_rden <= 1'b0;

//波形有效显示区域标志位
//wire wave_dis = wave_disp & (y_dis >= {2'd0,wave_ys}) & (y_dis <= {2'd0,wave_ye}) & (x_dis >= {2'd0,wave_xs}) & (x_dis <= {2'd0,wave_xe});
reg wave_dis; //波形有效显示区域标志位

always @(posedge clk or negedge rst_n)
if(!rst_n) wave_dis <= 1'b0;
else if((ycnt >= (VGA_VST+VGA_VBP+{2'd0,wave_ys})) && (ycnt < (VGA_VST+VGA_VBP+{2'd0,wave_ye})) &&
(xcnt >= {2'd0,wave_xs}+(VGA_HST+VGA_HBP-2)) && (xcnt < {2'd0,wave_xe}+(VGA_HST+VGA_HBP-2))) wave_dis <= 1'b1;
else wave_dis <= 1'b0;

////////////////////////////////////////////////////////////////////////////////
//液晶显示数据控制逻辑
////////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------
//显示数据处理输出
reg[15:0] lcd_dhqr;
reg[7:0] wave_datbusr; //波形值缓存一拍，用于连线

always @(posedge clk) begin
wave_datbusr <= wave_datbus;
end

//叠加层和波形处理
always @(posedge clk or negedge rst_n)
if(!rst_n) lcd_dhqr <= 16'd0;
else if(wave_dis) begin //波形显示区域
if((wave_datbusr == 8'd0) || (wave_datbus == 8'd0)) begin //X轴第1个点和最后1个点显示单点
//if(y_dis == (wave_ye-(wave_datbus-1'b1))) lcd_dhqr <= wave_fcor; //前景 {MOD}
if(ycnt == (VGA_VST+VGA_VBP)+({2'd0,wave_ye}-(wave_datbus-1'b1))) lcd_dhqr <= wave_fcor; //前景 {MOD}
else lcd_dhqr <= wave_bcor; //背景 {MOD}
end
else begin //X轴第1个点和最后1个点之间的显示连续的连线效果
if(wave_datbusr > wave_datbus) begin
//if((y_dis >= (wave_ye-(wave_datbusr-1'b1))) && (y_dis <= (wave_ye-(wave_datbus-1'b1)))) lcd_dhqr <= wave_fcor; //前景 {MOD}
if((ycnt >= (VGA_VST+VGA_VBP)+({2'd0,wave_ye}-(wave_datbusr-1'b1)))
&& (ycnt <= (VGA_VST+VGA_VBP)+({2'd0,wave_ye}-(wave_datbus-1'b1)))) lcd_dhqr <= wave_fcor; //前景 {MOD}
else lcd_dhqr <= wave_bcor; //背景 {MOD}
end
else begin
//if((y_dis >= (wave_ye-(wave_datbus-1'b1))) && (y_dis <= (wave_ye-(wave_datbusr-1'b1)))) lcd_dhqr <= wave_fcor; //前景 {MOD}
if((ycnt >= (VGA_VST+VGA_VBP)+({2'd0,wave_ye}-(wave_datbus-1'b1)))
&& (ycnt <= (VGA_VST+VGA_VBP)+({2'd0,wave_ye}-(wave_datbusr-1'b1)))) lcd_dhqr <= wave_fcor; //前景 {MOD}
else lcd_dhqr <= wave_bcor; //背景 {MOD}
end
end
end
else lcd_dhqr <= lcd_dhq;

//-----------------------------------------------------------
//显示数据处理输出
reg[15:0] lcd_mudb;

always @(posedge clk or negedge rst_n)
if(!rst_n) lcd_mudb <= 16'd0;
else if(lcd_dhqr == 16'h0000) lcd_mudb <= lcd_rfdb; //若叠加页数据为0x0000时，当前像素点为显示页数据
else lcd_mudb <= lcd_dhqr; //否则为叠加显示页数据

assign lcd_r = vga_valid ­ lcd_mudb[15:11]:5'd0;
assign lcd_g = vga_valid ­ lcd_mudb[10:5]:6'd0;
assign lcd_b = vga_valid ­ lcd_mudb[4:0]:5'd0;

//-----------------------------------------------------------
//液晶背光和时钟控制逻辑
assign lcd_en = mcu_ledon;
assign lcd_clk = ~clk;

endmodule

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11条回答
tongjingkuo
2019-07-17 10:51
 精彩回答 2  元偷偷看……0人看过

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