FPGA

锁相环（PLL）警告，求答

2019-07-15 23:28发布

站内问答 / FPGA
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Warning: PLL cross checking found inconsistent PLL clock settings:
        Warning: Node: inst|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000

Warning: Node: inclk0 was determined to be a clock but was found without an associated clock assignment.



想问下这是怎么回事，会不会影响正常使用

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7条回答
a中蓝
2019-07-16 02:46
寄存器没有初始化
你看下那上面的错误中几个寄存器再对着数据手册看下，我没这个手册不能给你看了。

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