module count
(
input clk,
input reset,
input zero,
output [23:0] num
);
//捕捉zero上升沿
reg zero_r1;
reg zero_r2;
always @ ( posedge clk or negedge reset )
if( !reset )
  begin
   zero_r1 <= 1'b0;
   zero_r2 <= 1'b0;
  end
else
  begin
   zero_r1 <= zero;
   zero_r2 <= zero_r1;
  end
//用来计数zero一个周期内有多少个时钟
reg [23:0] num_r;
reg [1:0] step;
always @ ( posedge clk or negedge reset )
if( !reset )
  begin
   num_r <= 24'd0;
   step <= 2'd0;
  end
else
  begin
   case( step )
   2'd0://等待zero上升沿到来
    if( zero_r1 && !zero_r2 )
     begin
      step <= step + 1'b1;
      num_r <= num_r + 1'b1;
     end
    else ;
   2'd1://计数
    if( zero_r1 && !zero_r2 )
     step <= step + 1'b1;
    else
     num_r <= num_r + 1'b1;
   endcase
  end
assign num = num_r；