Error (10500): VHDL syntax error at teltcl.vhd(5) near text "Â"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY teltcl is
port( Clk1 : in std_logic; --时钟输入50Mhz
TSTEN : out std_logic; --允许计数
clr1 : out std_logic; --计数器清零信号产生
--load : out std_logic); --锁存、显示输出允许
CLK5 : OUT STD_LOGIC );
end teltcl;
architecture behave of teltcl is
signal clk1hz :std_logic;--1HZ时钟信号
signal count :std_logic_vector(2 downto 0);--6秒计数
signal clr2 :std_logic;--清零信号
signal ena2 :std_logic;--允许计数信号
--signal load1 :std_logic;--允许计数信号
signal CLK6 :STD_LOGIC;
begin
process(clk1) --50MHZ信号产生
variable cnttemp : INTEGER RANGE 0 TO 999999;
begin
IF clk1='1' AND clk1'event THEN
IF cnttemp=999999 THEN cnttemp:=0;
ELSIF cnttemp<500000 THEN clk1hz<='1';
ELSE clk1hz<='0';
END IF;
cnttemp:=cnttemp+1;
END IF;
end if;
end process;
process(Clk1hz)--6秒计数
begin
if(Clk1hz'event and Clk1hz='1') then
count<=count+1;
if count<6 then
ena2<='1';clr2<='0';
elsif count=6 then
ena2<='0';clr2<='0';
elsif count=7 then
ena2<='0';clr2<='1';CLK6<='1';
end if;
end if;
tsten<=ena1;;clr1<=clr2;CLK5<=CLK6;
end process;
end behave;