本帖最后由 yatessss 于 2015-5-30 16:02 编辑
首先叙述一下 这个程序是一个PCM编码程序的一部分 [qq]861831106[/qq]
但是因为是初学 程序的很多地方看不懂 不知道每个子程序的作用
程序的注释 我用中文表明了
我想请问一下 有没有会的大神 能够讲解一下 每一个子程序的作用是什么 谢谢!!! 谢谢帮助!!!!
下面是主程序的RTL图 和 最后那个程序的
电路图
主程序————————————————————————————————————————————————————————————library ieee;
use ieee.std_logic_1164.all;
en
tity alaw_l_nl is
port(
data :in std_logic_vector(12 downto 0); --pcm linear signal线性pcm信号
clock :in std_logic; --system clock系统时钟
frame :in std_logic; --frame synchronous signal帧同步信号
ebi :in std_logic; --enable even bit(a-law) inversion.1:inverted;0:not inverted
dataq :out std_logic); --output overlap signal输出信号重叠
end alaw_l_nl;
architecture structure of alaw_l_nl is
COMPONENT alaw_13_8
PORT(
data :in std_logic_vector(12 downto 0); --linear signal 线性信号
frame :in std_logic; --frame synchronous signal帧同步信号
dataq :out std_logic_vector(7 downto 0)); --output nolinear signal输出非线性信号
END COMPONENT;
COMPONENT alaw_invert
PORT(
data :in std_logic_vector(7 downto 0); --pcm nolinear signalpcm非线性信号
-- frame :in std_logic; --frame synchronous signal帧同步信号
ebi :in std_logic; --enable even bit(a-law) inversion.1:inverted;0:not inverted
dataq :out std_logic_vector(7 downto 0)); --output inversion signal反转信号输出
END COMPONENT;
COMPONENT p_s
PORT(
data :in std_logic_vector(7 downto 0); --pcm linear signal线性pcm信号
clock :in std_logic; --clock signal时钟信号
frame :in std_logic; --frame signal帧信号
dataq :out std_logic); --output overlap signal输出信号重叠
END COMPONENT;
signal data_p_s,data_invert :std_logic_vector(7 downto 0);
begin
u1:alaw_13_8
port map(data => data,
frame => frame,
dataq => data_invert);
u2:alaw_invert
port map(data => data_invert,
-- frame => frame,
ebi => ebi,
dataq => data_p_s);
u3:p_s
port map(data => data_p_s,
clock => clock,
frame => frame,
dataq => dataq);
end structure;
子程序1————————————————————————————————————————————————————————————
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
entity alaw_13_8 is
PORT(
data :in std_logic_vector(12 downto 0); --pcm linear signal
frame :in std_logic; --frame synchronous signal
dataq :out std_logic_vector(7 downto 0)); --output noliear signal
end alaw_13_8;
architecture rtl of alaw_13_8 is
signal data_in :std_logic_vector(6 downto 0);
begin
process(data)
begin
if data(11) = '1' then
data_in <= "111" & data(10 downto 7);
elsif data(10) = '1' then
data_in <= "110" & data(9 downto 6);
elsif data(9) = '1' then
data_in <= "101" & data(8 downto 5);
elsif data(8) = '1' then
data_in <= "100" & data(7 downto 4);
elsif data(7) = '1' then
data_in <= "011" & data(6 downto 3);
elsif data(6) = '1' then
data_in <= "010" & data(5 downto 2);
elsif data(5) = '1' then
data_in <= "001" & data(4 downto 1);
else
data_in <= "000" & data(4 downto 1);
end if;
end process;
process(frame)
begin
if frame'event and frame = '1' then
dataq <= data(12) & data_in;
end if;
end process;
end rtl;
子程序2————————————————————————————————————————————————————————
library ieee;
use ieee.std_logic_1164.all;
entity alaw_invert is
port(
data :in std_logic_vector(7 downto 0); --pcm signal a
ebi :in std_logic; --enable even bit(a-law) inversion.1:inverted;0:not inverted
dataq :out std_logic_vector(7 downto 0)); --output overlap signal
end alaw_invert;
architecture rtl of alaw_invert is
begin
dataq <= data(7) & (not data(6)) & data(5) & (not data(4)) & data(3) & (not data(2)) & data(1) & (not data(0)) when ebi = '1' else "ZZZZZZZZ";
dataq <= data when ebi = '0' else "ZZZZZZZZ";
-- dataq <= data(7) & (not data(6)) & data(5) & (not data(4)) & data(3) & (not data(2)) & data(1) & (not data(0)) when ebi = '1' else
-- data ;
end rtl;
子程序3————————————————————————————————————————————————————————
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity p_s is
PORT(
data :in std_logic_vector(7 downto 0); --8bit parallel signal
clock :in std_logic; --clock signal
frame :in std_logic;
dataq :out std_logic); --output serial signal
end p_s;
architecture rtl of p_s is
signal data_pre :std_logic_vector(7 downto 0);
signal counter :std_logic_vector(2 downto 0);--integer range 7 downto 0 ;
begin
process(clock,frame)
begin
if frame = '1' then
counter <= "000";
elsif clock'event and clock = '1' then
counter <= counter + '1';
end if;
end process;
process(frame)
begin
if frame'event and frame = '1' then
data_pre <= data;
end if;
end process;
with counter select
dataq <= data_pre(7) when "000",
data_pre(6) when "001",
data_pre(5) when "010",
data_pre(4) when "011",
data_pre(3) when "100",
data_pre(2) when "101",
data_pre(1) when "110",
data_pre(0) when others;
end rtl;
另外程序————————————————————————————————————————————————————————————
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alaw_overlap is
port(
dataa :in std_logic_vector(12 downto 0); --pcm signal a
datab :in std_logic_vector(12 downto 0); --pcm signal b
frame :in std_logic;
dataq :out std_logic_vector(12 downto 0)); --output overlap signal
end alaw_overlap;
architecture rtl of alaw_overlap is
signal sign :std_logic; --sign bit
signal xor_sign :std_logic; --xor sign bit
signal sel_sign :std_logic; --compare a and b
signal sel_code_a :std_logic; --select a or un_a
signal sel_code_b :std_logic; --select b or un_b
signal un_a :std_logic_vector(11 downto 0); --not a[n-2..0]
signal un_b :std_logic_vector(11 downto 0); --not b[n-2..0]
signal code_a :std_logic_vector(11 downto 0); --code_a[n-2..0]
signal code_b :std_logic_vector(11 downto 0); --code_b[n-2..0]
signal code :std_logic_vector(11 downto 0); --code[n-2..0]
signal integer_a :integer range 4095 downto 0;
signal integer_b :integer range 4095 downto 0;
signal code_tmp :std_logic_vector(12 downto 0); --code_a[n-2..0]
signal dataq_in :std_logic_vector(12 downto 0);
begin
integer_a <= conv_integer(dataa(11 downto 0)); --convert dataa to integer type;
integer_b <= conv_integer(datab(11 downto 0)); --convert datab to integer type;
un_a <= not dataa(11 downto 0) + '1';
un_b <= not datab(11 downto 0) + '1';
sel_sign <= '1' when integer_a > integer_b else
'0';
sign <= dataa(12) when sel_sign = '1' else
datab(12);
xor_sign <= dataa(12) xor datab(12);
sel_code_a <= xor_sign and (not sel_sign);
sel_code_b <= xor_sign and sel_sign;
code_a <= dataa(11 downto 0) when sel_code_a = '0' else un_a;
code_b <= datab(11 downto 0) when sel_code_b = '0' else un_b;
code_tmp <= ('0' & code_a) + ('0' & code_b) ;
code <= code_tmp(11 downto 0) when code_tmp(12) = '0' or xor_sign = '1' else
"111111111111";
dataq_in <= dataa when datab = "0000000000000" else
-- dataq <= datab when dataa = "0000000000000" else
sign & code;
process(frame)
begin
if rising_edge(frame) then
dataq <= dataq_in;
end if;
end process;
end rtl;
————————————————————————————————————————————————————————————————
首先叙述一下 这个程序是一个PCM编码程序的一部分 [qq]861831106[/qq]
但是因为是初学 程序的很多地方看不懂 不知道每个子程序的作用
程序的注释 我用中文表明了
我想请问一下 有没有会的大神 能够讲解一下 每一个子程序的作用是什么 谢谢!!! 谢谢帮助!!!!
下面是主程序的RTL图 和 最后那个程序的
电路图
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