LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENtiTY EVEN_DIVIDER IS
GENERIC(N:INTEGER :=8);
PORT(
CLKIN: IN STD_LOGIC;
CLKOUT:OUT STD_LOGIC;
CNT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END EVEN_DIVIDER;

ARCHITECTURE RTL OF EVEN_DIVIDER IS
SIGNAL COUNT:INTEGER;
BEGIN
该程序实现8分频，送入输入时钟，输出时钟恒为’1‘，请问为何