程序如下:
module chuangxinjijin(
clk_50M,rst_n,
count1,count2,
SP
);
input clk_50M,rst_n;
output reg [16:0] count1;
output reg [14:0] count2;
output reg SP;
//-----------------------------SP-------------------------------------
reg clear;
always @(negedge clk_50M or negedge rst_n)
if(!rst_n)
count1 <= 1'b0;
else if(count1==59996 )
begin
clear <= 1;
count1 <= 1'b0;
end
else
begin
count1 <= count1 + 1'b1;
clear <= 0;
end
//--------------------------------------------------------------
always @(negedge clk_50M or negedge rst_n)
if(!rst_n)
count2 <= 1'b0;
else if(coun2>=0 && count2<281)
begin
SP <= 1'b0;
count2 <= count2 + 1'b1;
end
else if(count2>=281 && count2<286 )
begin
SP <= 1'b1;
count2 <= count2 + 1'b1;
end
else if(count2>=286 && count2<330)
begin
SP <= 1'b0;
count2 <= count2 + 1'b1;
end
else if (count2 == 330)
count2 <= 281;
else if (clear == 1)
count2 <= 0;
else
count2 <= count2 + 1'b1;
endmodule
问题如下,为什么在clear为1,也就四count1计数到59996时,count2不为0哇
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不好意思,回复那么晚,这种改法会报错!
Error (10200): Verilog HDL Conditional Statement error at chuangxinjijin.v(207): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
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