FPGA

调用模块DDR3 UniPHY 问题

2019-07-16 00:24发布

站内问答 / FPGA
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tica, Arial, sans-serif">用Megawizard例化一个DDR3 SDRAM CONTROL UNIPHY模块 ,但是编译时，一直报错，
Error (174068): Output buffer atom "ddr3_I_settingdr3_I|unimaster_ver_0002:unimaster_ver_inst|unimaster_ver_p0:p0|unimaster_ver_p0_controller_phy:controller_phy_inst|unimaster_ver_p0_memphy_top:memphy_top_inst|unimaster_ver_p0_memphy:umemphy|unimaster_ver_p0_new_io_pads:uio_pads|unimaster_ver_p0_altdqdqsq_ddio[0].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|pad_gen[0].data_out" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination.
Error (174068): Output buffer atom "ddr3_I_settingdr3_test_I|unimaster_verdr3_I|unimaster_ver_0002:unimaster_ver_inst|unimaster_ver_p0:p0|unimaster_ver_p0_controller_phy:controller_phy_inst|unimaster_ver_p0_memphy_top:memphy_top_inst|unimaster_ver_p0_memphy:umemphy|unimaster_ver_p0_new_io_pads:uio_pads|unimaster_ver_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|pad_gen[0].data_out" has port "PARALLELTERMINATIONCONTROL[13]" connected, but does not use calibrated on-chip termination

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10条回答
terran910
2019-07-16 23:08
@in3ity  第一步：添加qip文件
                       方法：assignments>>settings>>file>>添加生成IP文件夹里的.qip文件
            第二步：运行pin_assignments.tcl文件
                       方法：tools>>Tcl Scripts...>>选择后缀为*_pin_assignments.tcl文件>>运行

     亲测问题已解决

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