FPGA

quartus编译错误

2019-07-16 00:26发布

站内问答 / FPGA
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代码如下
  1. --2shuruyufeimen
  2. library ieee;
  3. use ieee.std_logic_1164.all;
  4. entity nand2 is
  5.         port(a,b: in std_logic;
  6.                  y:out std_logic);
  7. end entity nand2;
  8. architecture nand22 of nand2 is
  9. begin
  10. y<=a NAND b;
  11. end architecture nand22;

  13. --3shuruyufeimen
  14. library ieee;
  15. use ieee.std_logic_1164.all;
  16. entity nand3 is
  17.         port(a,b,c: in std_logic;
  18.                  y:out std_logic);
  19. end entity nand3;
  20. architecture nand33 of nand3 is
  21. begin
  22. y<=NOT(a AND b AND c);
  23. end architecture nand33;

  25. --3shurubiaojueqi
  26. library ieee;
  27. use ieee.std_logic_1164.all;
  28. entity nand4 is
  29.         port(ain,bin,cin: in std_logic;
  30.                  yout:out std_logic);
  31. end entity nand4;
  32. architecture nand44 of nand4 is
  33. component nand2
  34.         port(a,b: in std_logic;
  35.                  y:out std_logic);
  36. end component nand2;
  37. component nand3
  38.         port(a,b,c: in std_logic;
  39.                  y:out std_logic);
  40. end component nand3;
  41. signal e,f,g:std_logic;
  42. begin
  43. u1:nand2 port map(a>=ain,b>=bin,y>=e);
  44. u2:nand2 port map(a>=ain,b>=cin,y>=f);
  45. u3:nand2 port map(a>=bin,b>=cin,y>=g);
  46. u4:nand3 port map(a>=e,b>=f,c>=g,y>=yout);
  47. end architecture nand44;
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错误显示  object a，b，c  is used but not declared
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2条回答
www5201006
2019-07-16 04:01
写的是三输入多数表决器

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