本帖最后由 wzh212 于 2014-6-3 16:34 编辑
tica, Tahoma, Arial, sans-serif">WARNING:PhysDesignRules:372 - Gated clock. Clock net rd_en is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
- reg rd_en;
-
- always @(*)
- begin
- rd_en <= ~csn && ~rdn;
- WR_RISING <= ~csn && ~wrn;
- end
-
-
- always @(posedge rd_en)
- begin
- if(rd_en == 1)
- begin
- case(addr[2:0])
- 3'b000:data_reg <= ARM_FPGA_REG0;
- 3'b001:data_reg <= ARM_FPGA_REG1;
- 3'b010:data_reg <= ARM_FPGA_REG2;
- 3'b011:data_reg <= ARM_FPGA_REG3;
- 3'b100:data_reg <= ARM_FPGA_REG4;
- 3'b101:data_reg <= ARM_FPGA_REG5;
- 3'b110:data_reg <= ARM_FPGA_REG6;
- 3'b111:data_reg <= ARM_FPGA_REG7;
- default:;
- endcase
- end
- end
复制代码
程序用到rd_en的地方,麻烦高手指点下,非常感谢![qq]1146254321[/qq]
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