新手刚刚开始学习FPGA。想做一个查表输出的正弦波。当用8个数据做初始化文件测试仿真的时候可以输出结果，但是我用64个正弦表的数据仿真时就会出错，测试程序上除了address的位宽其他都是一样的。找了好久都没找到问题，求给位前辈帮忙解答下。程序

LIBRARY ieee  ;
USE ieee.std_logic_unsigned.all  ;
USE ieee.std_logic_1164.all  ;
ENtiTY sin64_tb  IS
END ;

ARCHITECTURE one OF sin64_tb IS
  component sin64 is
      port(address                : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                                                clock                : IN STD_LOGIC ;
                                                q                : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
  end component sin64;         

    signal clock        : std_logic:='0';
    signal q: std_logic_vector(7 downto 0);
    signal        address1:        STD_LOGIC_VECTOR (5 DOWNTO 0):="000000";
     constant ClockPeriod: time := 40 ns;
begin
  process(clock)
  begin
   if        clock'event        and        clock        =        '1'        then        address1<=address1+1;
   end  if;
  end        process;

   process
    begin
           clock  <=  '0';
        wait for  clockperiod/2;
        clock  <=  '1';
        wait for  clockperiod/2;
    end process ;   
    u1: sin64 port map(clock=>clock,address=>address1,q=>q);
END ;



错误信息
# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at G:/quartus9.0/quartus/eda/sim_lib/altera_mf.vhd 39199 Subprogram read_my_memory
# called from  G:/quartus9.0/quartus/eda/sim_lib/altera_mf.vhd 40690 Process MEMORY