module fenpinqi(fout,clock,reset);
output fout;
input clock,reset;
integer i;
reg fout;
always @(posedge clock,reset)
begin
if(reset)
begin
i<=0;
fout<=0;
end
if(i==2)
begin
fout=~fout;
i<=i+1;
end
if(i==4)
begin
fout=~fout;
i<=0;
end
i<=i+1;
end
endmodule
这是测试
module fenpinqitest;
wire fout ;
reg clock,reset;
fenpinqi f(fout,clock,reset);
ini
tial
begin
clock=1'b0;
forever #20 clock=~clock;
end
initial
begin
reset=1'b1;
forever #100 reset=~reset;
end
endmodule
仿真
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