always @(posedge clk )
begin
if(!rst_n) count<={~D5,~D4,~D3,~D2,~D1};
else if(count<5'b11111) count<=count+1'b1;
else count<={~D5,~D4,~D3,~D2,~D1};
end
always @(posedge clk)
begin
if (count==5'b11111) clk_out<=1;
else clk_out<=0;
end
endmodule
示波器验证后没效果。请问5个按键控制分频系数这块该怎么写?
程序如下:
module div(clk,clk_out,rst_n,D1,D2,D3,D4,D5);
input clk; //系统时钟信号
input rst_n; //系统复位信
input wire D1,D2,D3,D4,D5;
output reg clk_out; //输出频率
reg[4:0] count;
always @(posedge clk )
begin
if(!rst_n) count<={~D5,~D4,~D3,~D2,~D1};
else if(count<5'b11111) count<=count+1'b1;
else count<={~D5,~D4,~D3,~D2,~D1};
end
always @(posedge clk)
begin
if (count==5'b11111) clk_out<=1;
else clk_out<=0;
end
endmodule
示波器验证后没效果。请问5个按键控制分频系数这块该怎么写?
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