library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
en
tity fenpin5 is
port(clkin, clr : in std_logic;
clkout : out std_logic
);
end entity fenpin5;
architecture behave of fenpin5 is
signal cnt1, cnt2 : std_logic_vector(3 downto 0);
signal temp1, temp2, temp : std_logic;
begin
temp <= temp1 and temp2;
clkout <= temp xor temp1;
process(clkin, clr)
begin
if(clr = '0') then
cnt1 <= "0000";
temp1 <= '0';
elsif(clkin'event and clkin = '1') then
if(cnt1 = "0100") then
cnt1 <= "0000";
else
cnt1 <= cnt1 + '1';
if( cnt1 < "0010") then
temp1 <= '0';
else
temp1 <= '1';
end if;
end if;
end if;
end process;
process(clkin, clr)
begin
if(clr = '0') then
cnt2 <= "0000";
temp2 <= '1';
elsif(clkin'event and clkin = '0') then
if(cnt2 = "0100") then
cnt2 <= "0000";
else
cnt2 <= cnt2 + '1';
if( cnt2 < "0010") then
temp2 <= '1';
else
temp2 <= '0';
end if;
end if;
end if;
end process;
end architecture behave;
懂的大神指导下
temp <= temp1 and temp2;
clkout <= temp xor temp1;
这两个语句分别得到的时序图是什么样的,我画了好几遍了,总是不对,总是低电平2.5个时钟,高电平1.5个时钟
能附图解释更好了,谢谢了
大神,讲解一下吧
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