# ** Error: C:/modeltech_10.1a/examples/tutorials/verilog/compare/test_sm.v(136): Module 'sm_seq' is not defined.
# ** Error: C:/modeltech_10.1a/examples/tutorials/verilog/compare/test_sm.v(138): Module 'beh_sram' is not defined.
# Op
timization failed
# Error loading design
如何解决?急!!!
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