library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
en
tity exa_10 is port
( inclk: in std_logic;
outled:out std_logic_vector(7 downto 0);
outbit:out std_logic_vector(7 downto 0));
end exa_10;
Architecture a_counter of exa_10 is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
signal lm ,hm: std_logic_vector(24 downto 0);
signal fpa,fpb: std_logic;
signal st: std_logic_vector(2 downto 0);
begin
process(inclk)
begin
if (inclk'event and inclk='1') then
if lm=24999999 then
lm<="0000000000000000000000000";
fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
process(inclk)
begin
if (inclk'event and inclk='1') then
if hm=50 then
hm<="0000000000000000000000000";
fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
process(fpa)
begin
if (fpa'event and fpa='1') then
if ma=9 then
ma<="0000";
if mb=5 then
mb<="0000";
if mc=9 then
mc<="0000";
if md=5 then
md<="0000";
if(me=2 and mf=1)then
me<="0001";mf<="0000";
else
if me=9 then
mf<=mf+1; me<="0000";
else
me<=me+1;
end if;
end if;
else
md<=md+1;
end if;
else
mc<=mc+1;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
end if;
end if;
end process;
process (fpb)
begin
if(fpb'event and fpb='1') then
st<=st+1;
end if;
end process;
process (st,ma,mb,mc,md,me,mf,mseg)
begin
case st is
when "000" =>
mseg<=ma;
outbit<="00000010";
when "001"=>
mseg<=mb;
outbit<="00100000";
when "010"=>
mseg<=mc;
outbit<="00010000";
when "011"=>
mseg<=md;
outbit<="00001000";
when "100"=>
mseg<=me;
outbit<="00000100";
when "101"=>
mseg<=mf;
outbit<="00000001";
when others=>outbit<="00000000";
end case;
end process;
Process(fpb)
begin
if(fpb'event and fpb='1') then
case mseg is
when "0001"=>outled<="00000110";
when "0010"=>outled<="01011011";
when "0011"=>outled<="01001111";
when "0100"=>outled<="01100110";
when "0101"=>outled<="01101101";
when "0110"=>outled<="01111101";
when "0111"=>outled<="00000111";
when "1000"=>outled<="01111111";
when "1001"=>outled<="01101111";
when "0000"=>outled<="00111111";
when "1010"=>outled<="01110111";
when "1011"=>outled<="01111100";
when "1100"=>outled<="00111001";
when "1101"=>outled<="01011110";
when "1110"=>outled<="01111001";
when "1111"=>outled<="01110001";
when others=>outled<="00111111";
end case;
end if;
end process;
end a_counter;
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