FPGA

PS2键盘时钟与系统时钟

2019-07-16 01:27发布

站内问答 / FPGA
6450 6 1506
请问一下，在编写ps2键盘程序时，键盘的时钟和系统时钟是什么关系？？？？
友情提示: 此问题已得到解决，问题已经关闭,关闭后问题禁止继续编辑，回答。
6条回答
yoonssica
2019-07-16 19:05
主宰自己 发表于 2013-7-30 12:32
不用管他，板子上有，你直接在顶层模块输入键盘时钟就好了

  2. <DIV class=blockcode>
  3. <BLOCKQUOTE>library IEEE;
  4. use IEEE.STD_LOGIC_1164.ALL;
  5. use IEEE.STD_LOGIC_ARITH.ALL;
  6. use IEEE.STD_LOGIC_UNSIGNED.ALL;

  8. entity ps2 is
  9. port (resetn: in std_logic; -- active low reset
  10. clock: in std_logic; -- system clock
  11. ps2_clk: in std_logic; -- PS/2 clock line
  12. ps2_dta: in std_logic; -- PS/2 data line
  13. hit_1: out std_logic;
  14. ascii: out std_logic_vector(7 downto 0)); -- LED outputs
  15. end ps2;

  17. architecture behavioral of ps2 is
  18. type state_type is (IDLE, START, DATA, PARITY); -- FSM states
  19. signal ps2_dv: std_logic; -- PS/2 data valid
  20. signal prv_ps2_clk, act_ps2_clk: std_logic; -- auxiliary signals
  21. signal recdata: std_logic_vector(7 downto 0); -- read data
  22. signal shift: std_logic; -- enable for shift reg.
  23. signal n_shift: std_logic; -- auxiliary signal
  24. signal latch: std_logic; -- latch read data
  25. signal n_latch: std_logic; -- auxiliary signal
  26. signal err: std_logic; -- parity or stop error
  27. signal n_err: std_logic; -- auxiliary signal
  28. signal parset: std_logic; -- preset for parity check
  29. signal n_parset: std_logic; -- auxiliary signal
  30. signal c_state, n_state: state_type; -- current & next states
  31. signal cntval: std_logic_vector(2 downto 0); -- counter of data bits
  32. signal zero: std_logic; -- counter is zero
  33. signal parbit: std_logic; -- odd parity of data
  34. signal leds:std_logic_vector(7 downto 0);
  35. signal hit_cnt:std_logic_vector(8 downto 0);
  36. signal hit:std_logic;
  37. begin
  38. -- Provides a one-shot pulse after every falling edge of PS/2 clock
  39. PS_CLK_SYNC: process(clock, resetn)
  40. begin
  41. if (resetn = '0') then
  42. prv_ps2_clk <= '1';
  43. act_ps2_clk <= '1';
  44. elsif (clock'event and clock = '1') then
  45. act_ps2_clk <= ps2_clk;
  46. prv_ps2_clk <= act_ps2_clk;
  47. end if;
  48. end process;
  49. ps2_dv <= (not act_ps2_clk) and prv_ps2_clk;

  51. -- Serial input, parallel output shift register
  52. SIPO: process(clock, resetn)
  53. begin
  54. if (resetn = '0') then
  55. recdata <= (others => '0');
  56. elsif (clock'event and clock = '1') then
  57. if (shift = '1') then
  58. recdata <= ps2_dta & recdata(7 downto 1);
  59. end if;
  60. end if;
  61. end process;

  63. -- Counter of data bits
  64. COUNT8: process(resetn, clock)
  65. begin
  66. if (resetn = '0') then
  67. cntval <= (others => '0');
  68. elsif (clock'event and clock = '1') then
  69. if (shift = '1') then
  70. cntval <= cntval + 1;
  71. end if;
  72. end if;
  73. end process;
  74. zero <= not (cntval(0) or cntval(1) or cntval(2));

  76. -- Parity check of received data
  77. PARITY_CHECK: process(clock, parset)
  78. begin
  79. if (parset = '1') then
  80. parbit <= '1';
  81. elsif (clock'event and clock = '1') then
  82. if (shift = '1' and ps2_dta = '1') then
  83. parbit <= not parbit;
  84. end if;
  85. end if;
  86. end process;

  88. -- Synchronous process of control state machine
  89. FSM_SYNC: process(clock, resetn)
  90. begin
  91. if (resetn = '0') then
  92. c_state <= IDLE;
  93. shift <= '0';
  94. latch <= '0';
  95. err <= '0';
  96. parset <= '1';
  97. elsif (clock'event and clock = '1') then
  98. c_state <= n_state;
  99. shift <= n_shift;
  100. latch <= n_latch;
  101. err <= n_err;
  102. parset <= n_parset;
  103. end if;
  104. end process;

  106. -- Combinatorial process of control state machine
  107. FSM_COMB: process(c_state, ps2_dv, ps2_dta, zero)
  108. begin -- default values
  109. n_shift <= '0';
  110. n_latch <= '0';
  111. n_err <= '0';
  112. n_parset <= '0';
  113. case c_state is -- wait to receive data
  114. when IDLE => if ((ps2_dv and (not ps2_dta)) = '1') then
  115. n_state <= START;
  116. n_parset <= '1';
  117. else
  118. n_state <= IDLE;
  119. end if;
  120. -- receive first data bit
  121. when START => if (ps2_dv = '0') then
  122. n_state <= START;
  123. else
  124. n_state <= DATA;
  125. n_shift <= '1';
  126. end if;
  127. -- receive remaining data bits and parity
  128. when DATA => if (ps2_dv = '0') then
  129. n_state <= DATA;
  130. elsif (zero = '0') then
  131. n_state <= DATA;
  132. n_shift <= '1';
  133. else
  134. n_state <= PARITY;
  135. if (parbit /= ps2_dta) then
  136. n_err <= '1';
  137. end if;
  138. end if;
  139. -- receive stop bit
  140. when PARITY => if (ps2_dv = '0') then
  141. n_state <= PARITY;
  142. else
  143. n_state <= IDLE;
  144. n_latch <= '1';
  145. n_err <= not ps2_dta;
  146. end if;
  147. end case;
  148. end process;

  150. -- Output latch
  151. LED_OUTPUTS: process(resetn, clock)
  152. begin
  153. if (resetn = '0') then
  154. leds <= (others => '1');
  155. elsif (clock'event and clock = '1') then
  156. if (err = '1') then
  157. leds <= (others => '1');
  158. elsif (latch = '1') then
  159. leds <= recdata;
  160. end if;
  161. end if;
  162. end process;
  163. PROCESS(leds)
  164. BEGIN
  165. case leds is
  166. when "01000101"=> ascii <= "00110000"; hit<='1'; --0
  167. when "00010110"=> ascii <= "00110001"; hit<='1'; --1
  168. when "00011110"=> ascii <= "00110010"; hit<='1'; --2
  169. when "00100110"=> ascii <= "00110011"; hit<='1'; --3
  170. when "00100101"=> ascii <= "00110100"; hit<='1'; --4
  171. when "00101110"=> ascii <= "00110101"; hit<='1'; --5
  172. when "00110110"=> ascii <= "00110110"; hit<='1'; --6
  173. when "00111101"=> ascii <= "00110111"; hit<='1'; --7
  174. when "00111110"=> ascii <= "00111000"; hit<='1'; --8
  175. when "01000110"=> ascii <= "00111001"; hit<='1'; --9
  176. when "00011100"=> ascii <= "01100001"; hit<='1'; --a
  177. when "00110010"=> ascii <= "01100010"; hit<='1'; --b
  178. when "00100001"=> ascii <= "01100011"; hit<='1'; --c
  179. when "00100011"=> ascii <= "01100100"; hit<='1'; --d
  180. when "00100100"=> ascii <= "01100101"; hit<='1'; --e
  181. when "00101011"=> ascii <= "01100110"; hit<='1'; --f
  182. when "00110100"=> ascii <= "01100111"; hit<='1'; --g
  183. when "00110011"=> ascii <= "01101000"; hit<='1'; --h
  184. when "01000011"=> ascii <= "01101001"; hit<='1'; --i
  185. when "00111011"=> ascii <= "01101010"; hit<='1'; --j
  186. when "01000010"=> ascii <= "01101011"; hit<='1'; --k
  187. when "01001011"=> ascii <= "01101100"; hit<='1'; --l
  188. when "00111010"=> ascii <= "01101101"; hit<='1'; --m
  189. when "00110001"=> ascii <= "01101110"; hit<='1'; --n
  190. when "01000100"=> ascii <= "01101111"; hit<='1'; --o
  191. when "01001101"=> ascii <= "01110000"; hit<='1'; --p
  192. when "00010101"=> ascii <= "01110001"; hit<='1'; --q
  193. when "00101101"=> ascii <= "01110010"; hit<='1'; --r
  194. when "00011011"=> ascii <= "01110011"; hit<='1'; --s
  195. when "00101100"=> ascii <= "01110100"; hit<='1'; --t
  196. when "00111100"=> ascii <= "01110101"; hit<='1'; --u
  197. when "00101010"=> ascii <= "01110110"; hit<='1'; --v
  198. when "00011101"=> ascii <= "01110111"; hit<='1'; --w
  199. when "00100010"=> ascii <= "01111000"; hit<='1'; --x
  200. when "00110101"=> ascii <= "01111001"; hit<='1'; --y
  201. when "00011010"=> ascii <= "01111010"; hit<='1'; --z
  202. when "00111001"=> ascii <= "00100000"; hit<='1'; --spacebar
  203. when "01100110"=> ascii <= "00100000"; hit<='1'; --backspace
  204. when "01110001"=> ascii <= "11100000"; hit<='1'; --del
  205. when others => ascii <= "00100000"; hit<='0'; --' ' for unlisted characters.
  206. end case;
  207. if hit='1' then
  208. if hit_cnt="111111111" then
  209. hit_1<='1';
  210. hit_cnt<="000000000";
  211. else
  212. hit_cnt<=hit_cnt+1;
  213. end if;
  214. else
  215. hit_1<=hit;
  216. end if;
  217. END PROCESS;

  219. end behavioral;
复制代码这个程序里的 if (resetn = '0') then
prv_ps2_clk <= '1';
act_ps2_clk <= '1';
elsif (clock'event and clock = '1') then
act_ps2_clk <= ps2_clk;
prv_ps2_clk <= act_ps2_clk;
end if;

这个部分我不能理解，为什么是时钟的上升沿的时候进行那些操作？？？

一周热门 更多>