- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_ARITH.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- ENtiTY cnt4_2 IS
- PORT(pst,clk,rst,enable,load:IN STD_LOGIC;
- data:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- cnt:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
- END cnt4_2;
- ARCHITECTURE bev OF cnt4_2 IS
- BEGIN
- PROCESS(pst,clk,rst)
- BEGIN
- IF pst='1' THEN
- cnt<=(others=>'1');
- ELSIF rst='1' THEN
- cnt<=(others=>'0');
- ELSIF clk'EVENT AND clk='1' THEN
- IF load='1' THEN
- cnt<=data;
- ELSIF enable='1' THEN
- cnt<=cnt+1;
- END IF;
- END IF;
- END PROCESS;
- END bev;
复制代码这是四位二进制技术器的VHDL程序,请问ARITH这个包是做什么用的呢???还有,那个cnt<=(others=>'0'),这种写法就是others=>'0'这种用法是如何理解呢?
也就是相当于将cnt的每个位都付0呗???
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