fpga时序问题,大侠们帮帮忙吧!!!!!

2019-07-16 02:11发布

1.Warning: Can't achieve timing requirement Clock Setup: 'hh:inst1|k:inst6|altpll:altpll_component|_clk0' along 2504 path(s). See Report window for details.
2.Warning: Clock period specified in clock requirement for clock "hh:inst1|k:inst6|altpll:altpll_component|_clk0" must be greater than or equal to the I/O edge rate limit of 5.538 ns in the currently selected device
3.Warning: Can't achieve minimum setup and hold requirement hh:inst1|k:inst6|altpll:altpll_component|_clk0 along 209 path(s). See Report window for details.
这是一个程序的警告信息,这种该怎么解决。时序约束的资料我已经看了很多,可以用timequest写max 。min等时序约束。但就是不知道遇到问题该从哪里下手,有没有具体讲时序约束例子的书籍吗??顺便推荐下吧》》
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