module test5(
count,
clk,
rst,
data_out
);
input clk, rst;
output data_out;
output count;
reg [2:0] count = 0;
wire [7:0] data_out;
ip_rom IP_ROM(
.address(count),
.clock(clk),
.q(data_out)
);
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
count <= 0;
end
else
begin
count <= count + 1;
end
end
endmodule
//////////////////////////////////////////////////主程序
`
timescale 1 ns/ 1 ps
module test5_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst;
// wires
wire [2:0] count;
wire [7:0] data_out;
// assign statements (if any)
test5 i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.count(count),
.data_out(data_out),
.rst(rst)
);
initial
begin
rst = 1;
#10 rst = 0;
clk = 1;
end
always
begin
#100 clk = ~clk;
end
endmodule
/////////////////////////////////////////////test bench
刚开始学
FPGA 很多东西都不懂 这个也才刚开始看
仿真波形能看出有的地方挤在一起,能看出来仿真结果是不对的,但不知道哪里出了问题。
-
wire [7:0] data_out;
这两句不对吧!
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