本帖最后由 L‰Ζ权℃ミ/jd 于 2012-2-29 17:42 编辑

下面的程序哪里出现错误啊，帮忙改下。不要引入clk做监控，直接用inc,dec在敏感列表。
module opt_square(inc,dec,high);
  input inc,dec;
  output reg[6:0] high;
  always@( posedge inc or posedge dec )
    begin
      if(inc) high<=high+7'b1;
      else high<=high-7'b1;
    end
endmodule

主要想实现2个按键的加一和减一。
编译通得过，在产生功能仿真网表是，提示成功，但是进度在99%

进行波形仿真后出现很多错误。
怎样修改，出现什么问题？求助啊
Error: Zero-time oscillation in node "|opt_square|high[0]~reg0" at time 180.0 ns. Check the design or vector source file for combinational loop.
Error: Zero-time oscillation in node "|opt_square|high[0]" at time 180.0 ns. Check the design or vector source file for combinational loop.
Error: Zero-time oscillation in node "|opt_square|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]~7" at time 180.0 ns. Check the design or vector source file for combinational loop.
Error: Zero-time oscillation in node "|opt_square|lpm_add_sub:Add1|addcore:adder|_~17" at time 180.0 ns. Check the design or vector source file for combinational loop.
Error: Zero-time oscillation in node "|opt_square|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0" at time 180.0 ns. Check the design or vector source file for combinational loop.
Error: Zero-time oscillation in node "|opt_square|lpm_add_sub:Add0|addcore:adder|_~0" at time 180.0 ns. Check the design or vector source file for combinational loop.
Error: Zero-time oscillation in node "|opt_square|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]" at time 180.0 ns. Check the design or vector source file for combinational loop.
Error: Zero-time oscillation in node "|opt_square|lpm_add_sub:Add1|addcore:adder|_~24" at time 180.0 ns. Check the design or vector source file for combinational loop.
Error: Zero-time oscillation in node "|opt_square|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]" at time 180.0 ns. Check the design or vector source file for combinational loop.

而且进行时序仿真的时候能出现波形，但是波形是错误的