library ieee;
use ieee.std_logic_1164.all;
entity dengdai is
port(clk: in std_logic;
     reset: in std_logic;
     d:in std_logic;
     q:out std_logic);
     end dengdai;
     architecture one of dengdai is
     begin
     process
     begin
     if reset='1'then q<='0';
     elsif clk'event and clk='1'then
     q<=d;
     end if;
     wait on clk,reset  ;
   
     end process;
     end one;
这个程序报错为Error (10533): VHDL Wait Statement error at dengdai.vhd(17): Wait Statement must contain condition clause with UNTIL keyword