TI

TMS320F28335 FFT后发现与真实幅值差别很大

2019-07-17 15:54发布

站内问答 / TI MCU
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本帖最后由 williamzjy 于 2017-4-5 14:48 编辑
  1. 用TMSF28335的ADC模块以8.3MHz的采样率采样函数发生器产生的24KHz正弦波（0--2V）做FFT分析验证,现发现采样是准确的，运算的频点分布也是正确的，可是FFT后的RFFTmagBuff怎么和真实的信号幅值对不上啊，直流分量1V，信号幅值1V，不知道我理解的对不对，
  2. 还有就是
  3. RFFT_adc_f32u(&rfft_adc);   // This version of FFT doesn't need buffer alignment这个和RFFT_f32u(&rfft_adc)有什么区别，我同时还发现AdcMirror.ADCRESULT0不用右移4位了，本身就是右对齐的，之前右移四位，运算完全是0，求各位指点怎么和信号真实幅值对上，好像*2/N也不对啊。。。表示疑惑
  4. /*采样不连续率提高到8.3M，之前的不准确，连续采样可以有8.3M的采样率 2017.03.19*/
  5. #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
  6. #include "DSP2833x_Examples.h" // DSP2833x Examples Include File

  8. #include "DSP28x_Project.h" // Device Headerfile and Examples Include File
  9. #include "math.h"
  10. #include "fpu_rfft.h"

  12. #define RFFT_STAGES 10
  13. #define RFFT_SIZE (1 << RFFT_STAGES)

  15. #define ADC_BUF_LEN RFFT_SIZE // ADC buffer length
  16. //#define ADC_SAMPLE_PERIOD 3124 // 3124 = (3125-1) = 48 KHz sampling w/ 150 MHz SYSCLKOUT

  18. #define F_PER_SAMPLE 8300000.0L/(float)RFFT_SIZE //Internal sampling rate is 48kHz

  20. RFFT_ADC_F32_STRUCT rfft_adc;
  21. RFFT_F32_STRUCT rfft;

  23. float RFFToutBuff[RFFT_SIZE]; //Calculated FFT result
  24. float RFFTF32Coef[RFFT_SIZE]; //Coefficient table buffer
  25. float RFFTmagBuff[RFFT_SIZE/2+1]; //Magnitude of frequency spectrum

  27. //--- Global Variables
  28. //uint16_t AdcBuf[ADC_BUF_LEN]; // ADC buffer allocation

  30. volatile uint16_t FFTStartFlag = 0; // One frame data ready flag



  34. // ADC start parameters
  35. #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT
  36. #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
  37. #endif
  38. #if (CPU_FRQ_100MHZ)
  39. #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
  40. #endif

  42. #define CPU_FREQ 150E6
  43. #define LSPCLK_FREQ CPU_FREQ/4
  44. #define SCI_FREQ 115200
  45. #define SCI_PRD (LSPCLK_FREQ/(SCI_FREQ*8))-1

  47. interrupt void sciaRxFifoIsr(void);
  48. void scia_fifo_init(void);
  49. void scia_xmit(int a);
  50. void scia_msg(Uint16 *msg);

  52. Uint16 sdataA[160]; // Send data for SCI-A
  53. Uint16 rdataA[160]; // Received data for SCI-A


  56. #define ADC_CKPS 0x0 // ADC module clock = HSPCLK/1 = 25.5MHz/(1) = 25.0 MHz
  57. #define ADC_SHCLK 0x1 // S/H width in ADC module periods = 2 ADC cycle
  58. //#define BUF_SIZE 160 // Sample buffer size

  60. // Global variable for this example
  61. //Uint16 j = 0,ADC_END = 0; // ADC finish flag

  63. //#pragma DATA_SECTION(ADC_Result,"DMARAML4");
  64. //volatile float ADC_Result[160];

  66. #pragma DATA_SECTION(AdcBuf,"DMARAML6L7");
  67. //volatile Uint16 AdcBuf[ADC_BUF_LEN];
  68. uint16_t AdcBuf[ADC_BUF_LEN];
  69. float AdcBuf2[ADC_BUF_LEN];

  71. volatile Uint16 *DMADest;
  72. volatile Uint16 *DMASource;
  73. interrupt void local_DINTCH1_ISR(void);



  77. main()
  78. {
  79. uint16_t i,j;
  80. float freq; // Frequency of single-frequency-component signal

  82. InitSysCtrl();
  83. InitSciaGpio();

  85. EALLOW;
  86. SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
  87. EDIS;


  90. DINT;

  92. InitPieCtrl();

  94. // Disable CPU interrupts and clear all CPU interrupt flags:
  95. IER = 0x0000;
  96. IFR = 0x0000;

  98. InitPieVectTable();

  100. // #ifdef FLASH
  101. // MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
  102. // InitFlash();
  103. // #endif

  105. // Interrupts that are used in this example are re-mapped to
  106. // ISR functions found within this file.
  107. EALLOW; // Allow access to EALLOW protected registers
  108. PieVectTable.DINTCH1= &local_DINTCH1_ISR;
  109. PieVectTable.SCIRXINTA = &sciaRxFifoIsr;

  111. EDIS; // Disable access to EALLOW protected registers

  113. rfft_adc.Tail = &rfft.OutBuf; //Link the RFFT_ADC_F32_STRUCT to
  114. //RFFT_F32_STRUCT. Tail pointer of
  115. //RFFT_ADC_F32_STRUCT is passed to
  116. //the OutBuf pointer of RFFT_F32_STRUCT
  117. rfft.FFTSize = RFFT_SIZE; //Real FFT size
  118. rfft.FFTStages = RFFT_STAGES; //Real FFT stages
  119. rfft_adc.InBuf = &AdcBuf[0]; //Input buffer
  120. rfft.OutBuf = &RFFToutBuff[0]; //Output buffer
  121. rfft.CosSinBuf = &RFFTF32Coef[0]; //Twiddle factor
  122. rfft.MagBuf = &RFFTmagBuff[0]; //Magnitude output buffer

  124. RFFT_f32_sincostable(&rfft); //Calculate twiddle factor

  126. //Clean up output buffer
  127. for (i=0; i < RFFT_SIZE; i++)
  128. {
  129. RFFToutBuff[i] = 0;
  130. }

  132. //Clean up magnitude buffer
  133. for (i=0; i < RFFT_SIZE/2+1; i++)
  134. {
  135. RFFTmagBuff[i] = 0;
  136. }


  139. scia_fifo_init(); // Init SCI-A

  141. // EnableInterrupts();
  142. PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
  143. PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, int1


  146. PieCtrlRegs.PIEIER7.bit.INTx1 = 1;
  147. IER |= 0x100; // Enable CPU INT
  148. IER |= M_INT7 ; //Enable INT7 (7.1 DMA Ch1)

  150. EINT; // Enable Global interrupt INTM
  151. ERTM; // Enable Global realtime interrupt DBGM

  153. InitAdc(); // For this example, init the ADC

  155. // Specific ADC setup for this example:
  156. AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; // Sequential mode: Sample rate = 1/[(2+ACQ_PS)*ADC clock in ns]
  157. // = 1/(3*40ns) =8.3MHz (for 150 MHz SYSCLKOUT)
  158. // = 1/(3*80ns) =4.17MHz (for 100 MHz SYSCLKOUT)
  159. // If Simultaneous mode enabled: Sample rate = 1/[(3+ACQ_PS)*ADC clock in ns]
  160. AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
  161. AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode
  162. AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
  163. AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS)
  164. AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
  165. // AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;

  167. AdcRegs.ADCTRL1.bit.CONT_RUN = 1; // Setup continuous run

  169. AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0; // Enable Sequencer override feature

  171. AdcRegs.ADCCHSELSEQ1.all = 0x0; // Initialize all ADC channel selects to A0
  172. AdcRegs.ADCCHSELSEQ2.all = 0x0; // Initialize all ADC channel selects to A0
  173. AdcRegs.ADCCHSELSEQ3.all = 0x0; // Initialize all ADC channel selects to A0
  174. AdcRegs.ADCCHSELSEQ4.all = 0x0; // Initialize all ADC channel selects to A0

  176. AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 15; // convert and store in 8 results registers



  180. // Assumes ePWM1 clock is already enabled in InitSysCtrl();
  181. // EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
  182. EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
  183. EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
  184. EPwm1Regs.CMPA.half.CMPA = 150; // Set compare A value
  185. EPwm1Regs.TBPRD =300; // Set period for ePWM1
  186. EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start



  190. // EALLOW;
  191. /* 在 InitSysCtrl()中已经将ePWM1的时钟进行了使能 */
  192. /* 用来配置ADC的采样率 */

  194. // SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM

  196. /* ePWM1的相关配置,以供片内ADC的启动 */
  197. // EPwm1Regs.TBCTL.bit.CLKDIV = 0;
  198. // EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; /* TBCLK = SYSCLK/2 = 75MHz*/
  199. // EPwm1Regs.ETSEL.bit.SOCAEN = 1; /* 使能ADC开始转换A脉冲,使能ePWMxSOCA脉冲 */
  200. // EPwm1Regs.ETSEL.bit.SOCASEL = 4;/* 使能,ePWMxSOCA脉冲当定时器递增时时间基准计数器等于CMPA */
  201. // EPwm1Regs.ETPS.bit.SOCAPRD = 1; /* 在第一个事件上生成ePWMxSOCA脉冲 */

  203. // EPwm1Regs.TBPRD = 750; /* 设置时间基准计数器的周期,决定 PWM1的频率 */
  204. // EPwm1Regs.CMPA.half.CMPA = 150; // Set compare A value
  205. // EPwm1Regs.TBCTR = 0; /* 清空计数器 */
  206. // EPwm1Regs.TBCTL.bit.CTRMODE = 0; /* 设置计数器模式为递增计数模式 */
  207. // SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM

  209. // EDIS;



  213. // Initialize DMA
  214. DMAInitialize();

  216. // Clear Table
  217. for (i=0; i<ADC_BUF_LEN; i++)
  218. {
  219. AdcBuf[i] = 0x0000;
  220. }


  223. // Configure DMA Channel
  224. DMADest = &AdcBuf[0]; //Point DMA destination to the beginning of the array
  225. DMASource = &AdcMirror.ADCRESULT0; //Point DMA source to ADC result register base
  226. DMACH1AddrConfig(DMADest,DMASource);
  227. DMACH1BurstConfig(15,2,2);
  228. DMACH1TransferConfig(63,-14,2);
  229. DMACH1WrapConfig(600,600,600,600); //Don't use wrap function
  230. DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,SYNC_DISABLE,SYNC_SRC,
  231. OVRFLOW_DISABLE,THIRTYTWO_BIT,CHINT_END,CHINT_ENABLE);



  235. StartDMACH1();


  238. EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group

  240. while(1)
  241. {
  242. // Waiting ADC finish





  248. if(FFTStartFlag) // If one frame data ready, then do FFT
  249. {
  250. for (i=0; i<ADC_BUF_LEN; i++)
  251. {
  252. AdcBuf2[i] = (float)((AdcBuf[i]) * 3.0 / 4096.0);//不用右移4位了？之前一直右移4位，发现全是0
  253. }


  256. RFFT_adc_f32u(&rfft_adc); // This version of FFT doesn't need buffer alignment
  257. RFFT_f32_mag(&rfft); // Calculate spectrum amplitude

  259. j = 1;
  260. freq = RFFTmagBuff[1];
  261. for(i=2;i<RFFT_SIZE/2+1;i++)
  262. {
  263. //Looking for the maximum valude of spectrum magnitude
  264. if(RFFTmagBuff[i] > freq)
  265. {
  266. j = i;
  267. freq = RFFTmagBuff[i];
  268. }
  269. }

  271. freq = F_PER_SAMPLE * (float)j; //Convert normalized digital frequency to analog frequency

  273. FFTStartFlag = 0; //Start collecting the next frame of data
  274. EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
  275. AdcRegs.ADCTRL1.bit.CONT_RUN = 1;
  276. }


  279. }




  284. }

  286. // INT7.1
  287. interrupt void local_DINTCH1_ISR(void) // DMA Channel 1
  288. {

  290. // To receive more interrupts from this PIE group, acknowledge this interrupt
  291. DMADest = &AdcBuf[0]; //Point DMA destination to the beginning of the array
  292. DMASource = &AdcMirror.ADCRESULT0; //Point DMA source to ADC result register base
  293. EPwm1Regs.ETSEL.bit.SOCAEN = 0; // DISable SOC on A group
  294. AdcRegs.ADCTRL1.bit.CONT_RUN = 0;
  295. PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
  296. FFTStartFlag = 1; // One frame data ready
  297. // EPwm1Regs.TBCTL.bit.CTRMODE = 1; // count up and start
  298. // EPwm1Regs.TBCTR = 0; /* 清空计数器 */





  304. }

  306. interrupt void sciaRxFifoIsr(void)
  307. {
  308. // rdataA[0]=SciaRegs.SCIRXBUF.all; // Read data
  309. // scia_xmit(rdataA[0]);
  310. Uint16 i;

  312. for(i=0; i< 12; i++)
  313. {
  314. rdataA[i]=SciaRegs.SCIRXBUF.all; // Read data
  315. }

  317. for(i=0; i< 12; i++)
  318. {
  319. SciaRegs.SCITXBUF=rdataA[i]; // Send data
  320. }

  322. //SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
  323. SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
  324. PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack
  325. }

  327. void scia_fifo_init()
  328. {
  329. SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
  330. // No parity,8 char bits,
  331. // async mode, idle-line protocol
  332. SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
  333. // Disable RX ERR, SLEEP, TXWAKE
  334. SciaRegs.SCICTL2.bit.TXINTENA =1;
  335. SciaRegs.SCICTL2.bit.RXBKINTENA =1;
  336. SciaRegs.SCIHBAUD = 0x0000;
  337. SciaRegs.SCILBAUD = SCI_PRD;
  338. SciaRegs.SCICCR.bit.LOOPBKENA =0; // disEnable loop back
  339. SciaRegs.SCIFFTX.all=0xC021;
  340. SciaRegs.SCIFFRX.all=0x0021;//接收12个字节中断
  341. SciaRegs.SCIFFCT.all=0x00;

  343. SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
  344. SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
  345. SciaRegs.SCIFFRX.bit.RXFIFORESET=1;


  348. }


  351. // Transmit a character from the SCI
  352. void scia_xmit(int a)
  353. {
  354. while (SciaRegs.SCICTL2.bit.TXRDY == 0) {}
  355. SciaRegs.SCITXBUF=a;

  357. }


  360. void scia_msg(Uint16 * msg)
  361. {
  362. int i;
  363. i = 0;
  364. while(msg[i] != '')
  365. {
  366. scia_xmit(msg[i]);
  367. i++;
  368. }
  369. }

  371. //===========================================================================
  372. // No more.
  373. //===========================================================================

  375. </P>
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19条回答
uiint
2019-07-17 19:02
你的变量定义的对不对

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