module lab02(input clk,input clr,
output reg[6:0] b);
reg [3:0]q;
always@(posedge clk,negedge clr)
begin
if(!clr)
q<=4'b0000;
else
if (q==4'b1001)
q<=4'b0000;
else
q<=q+1'b1;
end
always@(q)
begin
case(q)
4'h0:b<=7'b1000000;
4'h1:b<=7'b1111001;
4'h2:b<=7'b0100100;
4'h3:b<=7'b0110000;
4'h4:b<=7'b0011001;
4'h5:b<=7'b0010010;
4'h6:b<=7'b0000010;
4'h7:b<=7'b1111000;
4'h8:b<=7'b0000000;
4'h9:b<=7'b0010000;
default:b<=7'b1111111;
endcase
end
endmodule语言环境：Quartus注意事项：文件命名XXX与module+XXX必须相同可以在本示例基础上实现多进制计数器
{var%20f='http://v.t.sina.com.cn/share/share.php?appkey=1515056452',u=z||d.location,p=['&url=',e(u),'&title=',e(t||d.title),'&source=',e(r),'&sourceUrl=',e(l),'&content=',c||'gb2312','&pic=',e(p||'')].join('');function%20a(){if(!window.open([f,p].join(''),'mb',['toolbar=0,status=0,resizable=1,width=440,height=430,left=',(s.width-440)/2,',top=',(s.height-430)/2].join('')))u.href=[f,p].join('');};if(/Firefox/.test(navigator.userAgent))setTimeout(a,0);else%20a();})(screen,document,encodeURIComponent,'','','https://www.xiaopingtou.cn//data/attach/topic/topicKPo7gB.jpg', '推荐 zhaohao8888 的文章《Verilog设计模十计数器》','https://www.xiaopingtou.net/article-52015.html','页面编码gb2312|utf-8默认gb2312'));){kind=link}