管脚定义
- 异步复位
reset
- 同步使能
en
- 同步清零
clr
- 计数器最大值状态指示
max_tick
- 当前数值
`timescale 1ns / 1ps
module mod_m_counter
#(
parameter M=10 // mod 10 by default
)
(
input wire clk,
input wire reset,//异步复位信号
input wire clr,//同步清零
input wire en,
output wire max_tick,
output wire [3:0] q
);
// signal declaration
localparam N = 4;
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// clk
always @(posedge clk, posedge reset) begin
if (reset) begin
r_reg <= 0;
end
else begin
r_reg <= r_next;
end
end
// next-state logic
assign r_next =
(clr || ((r_reg == (M-1)) && en) )? 4'b0 :
(
(en)? (r_reg+1) : r_reg
)
;
// output logic
assign q = r_reg;
assign max_tick = (r_reg == (M-1))? 1'b1:1'b0;
endmodule
源代码有修改,原始资料参考:
FPGA Protoyping by Verilog Examples, Pong P. Chu, 英文版, 第95页, 程序清单4.11
FPGA Protoyping by Verilog Examples. Xilinx Spartan™-3 Version