`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:04:55 08/13/2015
// Design Name:
// Module Name: Count60
// Project Name:
// Target Devices:
// Tool versions:
// Description: 同步60进制计数器,可输入初始计数值
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Count60(clk,rst_n,data_in,c_in,ctrol,q_out,c_out
);
//***********************
//delay declation
//***********************
parameter U_DLY=1;
//***********************
//input port
//***********************
input clk; //100mhz
input rst_n; //active low
input [5:0] data_in;
input c_in;
input ctrol; //ctrol=1 count from data_in;
//ctrol=0 count from 0;
//***********************
//output port
//***********************
output [5:0] q_out;
output c_out;
//***********************
//wire or reg declation
//***********************
reg [5:0] q_out;
reg c_out;
reg [5:0] data_in_cnt;
/////////////////////////////
//
//LOGIC
//
/////////////////////////////
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) begin
q_out <= #U_DLY 6'd0;
c_out <= #U_DLY 1'b0;
data_in_cnt <= 6'd0;
end
else begin
if(ctrol==1'b1) begin //count from data_in
q_out <= #U_DLY data_in +c_in+data_in_cnt;
if(q_out==6'd59)begin
q_out <= 6'd0;
c_out <= 1'b1;
data_in_cnt <= 6'd0;
end
else
data_in_cnt <= data_in_cnt +1'b1;
end //if(ctrol==1'b1) end
else begin//count from 0
if(q_out==6'd59)begin
q_out <= 6'd0;
c_out <= 1'b1;
end
else
q_out <= q_out +1'b1;
end //if(ctrol==1'b0) end
end //if(rst_n) end
end //--always end
endmodule
仿真可见,当输入初始值为10时,就会从10开始计数。可以通过ctrol来切换是否选择输入初始值。