library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ledcnt60 is
port(clk,clr,ena:in std_logic;
cnt10,cnt6:out std_logic_vector(3 downto 0);
carry_out:out std_logic;
led10:out std_logic_vector(6 downto 0);
led6:out std_logic_vector(6 downto 0));
end ledcnt60 ;
architecture behav of ledcnt60 is
signal cq6,cq10:std_logic_vector(3 downto 0);
begin
process(clk,clr,ena)is
begin
if clr='1' then
cq6<="0000";
cq10<="0000";
elsif clk'event and clk='1' then
if ena='1' then
if cq10="1001" then
cq10<="0000";
cq6<=cq6+'1';
else cq10<=cq10+'1';
end if;
if cq6="0101" and cq10="1001" then
cq6<="0000";
end if;
end if;
end if;
end process ;
process(cq6,clk)is
begin
if clk'event and clk='1' then
if cq6="0101" and cq10="1001" then carry_out<='1';
else carry_out<='0';
end if;
end if;
end process;
cnt10<=cq10;
cnt6<=cq6;
process(cq10)is
begin
case (cq10) is
when "0000" =>led10<="0111111";
when "0001" =>led10<="0000110";
when "0010" =>led10<="1011011";
when "0011" =>led10<="1001111";
when "0100" =>led10<="1100110";
when "0101" =>led10<="1101101";
when "0110" =>led10<="0111101";
when "0111" =>led10<="0000111";
when "1000" =>led10<="1111111";
when "1001" =>led10<="1100111";
when others =>led10<="0000000";
end case;
end process;
process(cq6)is
begin
case (cq6) is
when "0000" =>led6<="0111111";
when "0001" =>led6<="0000110";
when "0010" =>led6<="1011011";
when "0011" =>led6<="1001111";
when "0100" =>led6<="1100110";
when "0101" =>led6<="1101101";
when others =>led6<="0000000";
end case;
end process;
end behav;